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MT28F322D20FH-804BET Datasheet(PDF) 9 Page - Micron Technology |
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MT28F322D20FH-804BET Datasheet(HTML) 9 Page - Micron Technology |
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9 / 44 page  9 2 Meg x 16 Async/Page/Burst Flash Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28F322D20FH_4.p65 – Rev. 4, Pub. 7/02 ©2002, Micron Technology, Inc. 2 MEG x 16 ASYNC/PAGE/BURST FLASH MEMORY COMMAND STATE MACHINE (CSM) Commands are issued to the command state ma- chine (CSM) using standard microprocessor write tim- ings. The CSM acts as an interface between external microprocessors and the internal write state machine (WSM). The available commands are listed in Table 3, their definitions are given in Table 4, and their descrip- tions in Table 5. Program and erase algorithms are automated by an on-chip WSM. (For more specific information about the CSM transition states, see Micron technical note TN-28-33, “Command State Machine De- scription and Command Definition.” Once a valid PROGRAM/ERASE command is entered, the WSM executes the appropriate algorithm, which gen- erates the necessary timing signals to control the device internally to accomplish the requested operation. A com- mand is valid only if the exact sequence of WRITEs is completed. After the WSM completes its task, the WSM status bit (SR7) (see Table 7) is set to a logic HIGH level (1), allowing the CSM to respond to the full command set again. OPERATIONS Device operations are selected by entering a standard JEDEC 8-bit command code with conventional micro- processor timings into an on-chip CSM through I/Os DQ0–DQ7. The number of bus cycles required to activate a command is typically one or two. The first operation is always a WRITE. Control signals CE#, ADV#, and WE# must be at a logic LOW level (VIL), and OE# and RST# must be at logic HIGH (VIH). The second operation, when needed, can be a WRITE or a READ depending upon the command. During a READ operation, control signals CE#, ADV#, and OE# must be at a logic LOW level (VIL), and WE# and RST# must be at logic HIGH (VIH). Table 6 illustrates the bus operations for all the modes: write, read, reset, standby, and output disable. When the device is powered up, internal reset cir- cuitry initializes the chip to a read array mode of opera- tion. Changing the mode of operation requires that a command code be entered into the CSM. For each one of the two memory partitions, an on-chip status register is available. These two registers allow the progress of the various operations that can take place on a memory bank to be monitored. One of the two status registers is inter- rogated by entering a READ STATUS REGISTER com- mand onto the CSM (cycle 1), specifying an address within the memory partition boundary, and reading the register data on I/Os DQ0–DQ7 (cycle 2). Status register bits SR0- SR7 correspond to DQ0–DQ7 (see Table 7). COMMAND DEFINITION Once a specific command code has been entered, the WSM executes an internal algorithm, generating the nec- essary timing signals to program, erase, and verify data. See Table 4 for the CSM command definitions and data for each of the bus cycles. STATUS REGISTER The status register allows the user to determine whether the state of a PROGRAM/ERASE operation is pending or complete. The status register is monitored by toggling OE# and CE# and reading the resulting status code on I/Os DQ0–DQ7. The high-order I/Os (DQ8–DQ15) Table 3 Command State Machine Codes For Device Mode Selection COMMAND DQ0–DQ7 CODE ON DEVICE MODE 40h/10h Program setup/alternate program setup 20h Block erase setup 50h Clear status register 60h Protection configuration setup 60h Set read configuration register 70h Read status register 90h Read protection configuration register 98h Read query B0h Program/erase suspend C0h Protection register program/lock D0h Program/erase resume – erase confirm FFh Read array |
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