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EN6370 Datasheet(PDF) 2 Page - ON Semiconductor

Part # EN6370
Description  LCD Display Driver with Key Input Function
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Manufacturer  ONSEMI [ON Semiconductor]
Direct Link  http://www.onsemi.com
Logo ONSEMI - ON Semiconductor

EN6370 Datasheet(HTML) 2 Page - ON Semiconductor

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LC75808W
No.6370-2/38
Specifications
Absolute Maximum Ratings at Ta = 25
°C, VSS = 0V
Parameter
Symbol
Conditions
Ratings
Unit
VDD max
VDD
-0.3 to +7.0
Maximum supply voltage
VLCD max
VLCD
-0.3 to +12.0
V
VIN1
CE, CL, DI, INH
-0.3 to +7.0
VIN2
OSC, KI1 to KI5, TEST
-0.3 to VDD+0.3
Input voltage
VIN3
VLCD1, VLCD2, VLCD3, VLCD4
-0.3 to VLCD+0.3
V
VOUT1
DO
-0.3 to +7.0
VOUT2
OSC, KS1 to KS6, P1 to P4
-0.3 to VDD+0.3
Output voltage
VOUT3
VLCD0, S1 to S60, COM1 to COM10
-0.3 to VLCD+0.3
V
IOUT1
S1 to S60
300
μA
IOUT2
COM1 to COM10
3
IOUT3
KS1 to KS6
1
Output current
IOUT4
P1 to P4
5
mA
Allowable power dissipation
Pd max
Ta=85
°C
200
mW
Operating temperature
Topr
-40 to +85
°C
Storage temperature
Tstg
-55 to +125
°C
Allowable Operating Ranges at Ta = -40 to +85
°C, VSS = 0V
Ratings
Parameter
Symbol
Conditions
min
typ
max
unit
VDD
VDD
4.5
6.0
VLCD
VLCD, When the display contrast adjustment
circuit is used
7.0
11.0
Supply voltage
VLCD
VLCD , When the display contrast adjustment
circuit is not used
4.5
11.0
V
Output voltage
VLCD0
VLCD0
VLCD4
+4.5
VLCD
V
VLCD1
VLCD1
3/4(VLCD0
-VLCD4)
VLCD0
VLCD2
VLCD2
2/4(VLCD0
-VLCD4)
VLCD0
VLCD3
VLCD3
1/4(VLCD0
-VLCD4)
VLCD0
Input voltage
VLCD4
VLCD4
0
1.5
V
VIH1
CE, CL, DI, INH
0.8VDD
6.0
V
Input high level voltage
VIH2
KI1 to KI5
0.6VDD
VDD
V
Input low level voltage
VIL
CE, CL, DI, INH, KI1 to KI5
0
0.2VDD
V
Recommended external resistance
ROSC
OSC
43
k
Ω
Recommended external
capacitance
COSC
OSC
680
pF
Guaranteed oscillation range
fOSC
OSC
25
50
100
kHz
Data setup time
tds
CL, DI
[Figure 2]
160
ns
Data hold time
tdh
CL, DI
[Figure 2]
160
ns
CE wait time
tcp
CE, CL
[Figure 2]
160
ns
CE setup time
tcs
CE, CL
[Figure 2]
160
ns
CE hold time
tch
CE, CL
[Figure 2]
160
ns
High level clock pulse width
t
φH
CL
[Figure 2]
160
ns
Low level clock pulse width
t
φL
CL
[Figure 2]
160
ns
DO output delay time
tdc
DO RPU=4.7kΩ, CL=10pF *1
[Figure 2]
1.5
μs
DO rise time
tdr
DO RPU=4.7kΩ, CL=10pF *1
[Figure 2]
1.5
μs
Note: *1. Since DO is an open-drain output, these values depend on the resistance of the pull-up resistor RPU and the
load capacitance CL.
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.


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