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CS5210-1 Datasheet(PDF) 5 Page - ON Semiconductor |
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CS5210-1 Datasheet(HTML) 5 Page - ON Semiconductor |
5 / 8 page CS5210−1 http://onsemi.com 5 APPLICATION NOTES THEORY OF OPERATION The CS5210−1 linear regulator has a composite PNP−NPN output stage that requires an output capacitor for stability. A detailed procedure for selecting this capacitor is included in the Stability Considerations section. ADJUSTABLE OPERATION Design Guidelines This LDO adjustable regulator has an output voltage range of 1.25 V to 4.5 V. An external resistor divider sets the output voltage as shown in Figure 11. The regulator’s voltage sensing error amplifier maintains a fixed 1.25 V reference between the output pin and the adjust pin. A resistor divider network R1 and R2 causes a fixed current to flow to ground. This current creates a voltage across R2 that adds to the 1.25 V across R1 and sets the overall output voltage. The adjust pin current (typically 50 μA) also flows through R2 and adds a small error that should be taken into account if precise adjustment of VOUT is necessary. The output voltage is set according to the formula: VOUT + VREF R1 ) R2 R1 ) R2 IAdj The term IAdj × R2 represents the error added by the adjust pin current. R1 is chosen so that the minimum load current is at least 10 mA. R1 and R2 should be of the same composition for best tracking over temperature. The divider resistors should be placed as close to the IC as possible and connected to the output with a seperate metal trace. Figure 11. VIN CS5210−1 VOUT Adj R1 R2 While not required, a bypass capacitor connected between the adjust pin and ground will improve transient response and ripple rejection. A 0.1 μF tantalum capacitor is recommended for “first cut” design. Value and type may be varied to optimize performance vs price. The CS5210−1 linear regulator has an absolute maximum specification of 6.0 V for the voltage difference between VIN and VOUT. However, the IC may be used to regulate voltages in excess of 6.0 V. The main considerations in such a design are power−up and short circuit capability. In most applications, ramp−up of the power supply to VIN is fairly slow, typically on the order of several tens of milliseconds, while the regulator responds in less than one microsecond. In this case, the linear regulator begins charging the output capacitor as soon as the VIN to VOUT differential is large enough that the pass transistor conducts current. VOUT is essentially at ground, and VIN is on the order of several hundred millivolts, so the pass transistor is in dropout. As VIN increases, the pass transistor will remain in dropout, and current is passed to the load until VOUT is in regulation. Further increase in VIN brings the pass transistor out of dropout. The result is that the output voltage follows the power supply ramp−up, staying in dropout until the regulation point is reached. In this manner, any output voltage may be regulated. There is no theoretical limit to the regulated voltage as long as the VIN to VOUT differential of 6.0 V is not exceeded. However, the maximum ratings of the IC will be exceeded in a short circuit condition. Short circuit conditions will result in the immediate operation of the pass transistor outside of its safe operating area. Over−voltage stresses will then cause destruction of the pass transistor before overcurrent or thermal shutdown circuitry can become active. Additional circuitry may be required to clamp VIN to VOUT differential to less than 6.0 V if failsafe operation is required. One possible clamp circuit is illustrated in Figure 12; however, the design of clamp circuitry must be done on an application by application basis. Care must be taken to ensure the clamp actually protects the design. Components used in the clamp design must be able to withstand the short circuit conditions indefinitely while protecting the IC. Figure 12. VIN VOUT VAdj EXTERNAL SUPPLY |
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