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AR0331SRSC00XUEE0-DRBR1 Datasheet(PDF) 7 Page - ON Semiconductor |
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AR0331SRSC00XUEE0-DRBR1 Datasheet(HTML) 7 Page - ON Semiconductor |
7 / 72 page AR0331_DS Rev. L Pub. 5/15 EN 6 ©Semiconductor Components Industries, LLC, 2015. AR0331: 1/3-Inch 3.1 Mp/Full HD Digital Image Sensor General Description General Description The ON Semiconductor AR0331 can be operated in its default mode or programmed for frame size, exposure, gain, and other parameters. The default mode output is a 1080p- resolution image at 60 frames per second (fps). In linear mode, it outputs 12-bit or 10-bit A-Law compressed raw data, using either the parallel or serial (HiSPi) output ports. In high dynamic range mode, it outputs 12-bit compressed data using parallel output. In HiSPi mode, 12- or 14-bit compressed, or 16-bit linearized data may be output. The device may be operated in video (master) mode or in single frame trigger mode. FRAME_VALID and LINE_VALID signals are output on dedicated pins, along with a synchronized pixel clock in parallel mode. The AR0331 includes additional features to allow application-specific tuning: windowing and offset, auto black level correction, and on-board temperature sensor. Optional register information and histogram statistic information can be embedded in the first and last 2 lines of the image frame. The sensor is designed to operate in a wide temperature range (–30°C to +85°C). Functional Overview The AR0331 is a progressive-scan sensor that generates a stream of pixel data at a constant frame rate. It uses an on-chip, phase-locked loop (PLL) that can be optionally enabled to generate all internal clocks from a single master input clock running between 6 and 48 MHz. The maximum output pixel rate is 148.5 Mp/s, corresponding to a clock rate of 74.25 MHz. Figure 1 shows a block diagram of the sensor. Figure 1: Block Diagram Row noise correction Black level correction Adaptive CD filter Motion correction and Blue Halo filter HDR linearization (ME or DLO) Pixel defect correction Smooting filter Digital gain and pedestal Companding 16, 14, or 12 bits Parallel HiSPi 12 bits ( HDR and Linear), 12 or 10 bits Linear Test pattern generator ADC data |
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