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MT48LC1M16A1S Datasheet(PDF) 9 Page - Micron Technology |
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MT48LC1M16A1S Datasheet(HTML) 9 Page - Micron Technology |
9 / 51 page 16Mb: x16 SDRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. 16MSDRAMx16.p65 – Rev. 8/99 ©1999, Micron Technology, Inc. 9 16Mb: x16 SDRAM TRUTH TABLE 1 – COMMANDS AND DQM OPERATION (Notes: 1) NAME (FUNCTION) CS# RAS# CAS# WE# DQM ADDR DQs NOTES COMMAND INHIBIT (NOP) H X X X X X X NO OPERATION (NOP) L H H H X X X ACTIVE (Select bank and activate row) L L H H X Bank/Row X 3 READ (Select bank and column and start READ burst) L H L H L/H8 Bank/Col X 4 WRITE (Select bank and column and L H L L L/H8 Bank/Col Valid 4 start WRITE burst) BURST TERMINATE L H H L X X Active PRECHARGE (Deactivate row in bank or banks) L L H L X Code X 5 AUTO REFRESH or L L L H X X X 6, 7 SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER L L L L X Op-Code X 2 Write Enable/Output Enable –––– L – Active 8 Write Inhibit/Output High-Z –––– H – High-Z 8 following the Operation section; these tables provide current state/next state information. COMMANDS Truth Table 1 provides a quick reference of available commands. This is followed by a written description of each command. Three additional Truth Tables appear NOTE: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. A0-A10 and BA define the op-code written to the Mode Register. 3. A0-A10 provide row address, and BA determines which bank is made active. 4. A0-A7 provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA determines which bank is being read from or written to. 5. For A10 LOW, BA determines which bank is being precharged; for A10 HIGH, all banks are precharged and BA is a “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). |
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