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AR0542MBSC25SUD20 Datasheet(PDF) 11 Page - ON Semiconductor |
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AR0542MBSC25SUD20 Datasheet(HTML) 11 Page - ON Semiconductor |
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11 / 81 page  AR0542_DS Rev. H Pub. 5/15 EN 11 ©Semiconductor Components Industries, LLC, 2015. AR0542: 1/4-Inch CMOS Digital Image Sensor Signal Descriptions Signal Descriptions Table 3 provides signal descriptions for AR0542 die. For pad location and aperture infor- mation, refer to the AR0542 die data sheet. Table 3: Signal Descriptions Pad Name Pad Type Description EXTCLK Input Master clock input, 6–27 MHz. RESET_BAR Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers are restored to their factory default settings. XSHUTDOWN Input Asynchronous active LOW reset. When asserted, data output stops and all internal registers are restored to their factory default settings. This pin will turn off the digital power domain and is the lowest power state of the sensor. SCLK Input Serial clock for access to control and status registers. GPI[3:0] Input General purpose inputs. After reset, these pads are powered-down by default; this means that it is not necessary to bond to these pads. Any of these pads can be configured to provide hardware control of the standby, output enable, SADDR select, and shutter trigger functions. ON Semiconductor recommends that unused GPI pins be tied to DGND, but can also be left floating. TEST Input Enable manufacturing test modes. Connect to VDD_IO power for the MIPI-configured sensor. SDATA I/O Serial data from reads and writes to control and status registers. VCM_ISINK I/O Connected to VCM actuator. 100mA max. 3.3V max. VCM_GND I/O Connected to DGND. REG_OUT I/O 1.2V on-chip regulator output node. REG_IN I/O On-chip regulator input node. It needs to be connected to external 1.8V. REG_FB I/O This pad is receiving the 1.2V feedback from REG_OUT. It needs to be connected to REG_OUT. DATA0_P Output Differential MIPI (sub-LVDS) serial data (positive). DATA0_N Output Differential MIPI (sub-LVDS) serial data (negative). DATA1_P Output Differential MIPI (sub-LVDS) serial data 2nd lane (positive). Can be left floating when using one-lane MIPI serial interface. DATA1_N Output Differential MIPI (sub-LVDS) serial data second lane (negative). Can be left floating when using one-lane MIPI serial interface. CLK_P Output Differential MIPI (sub-LVDS) serial clock/strobe (positive). CLK_N Output Differential MIPI (sub-LVDS) serial clock/strobe (negative). LINE_VALID Output LINE_VALID (LV) output. Qualified by PIXCLK. FRAME_VALID Output FRAME_VALID (FV) output. Qualified by PIXCLK. DOUT[9:0] Output Parallel pixel data output. Qualified by PIXCLK. PIXCLK Output Pixel clock. Used to qualify the LV, FV, and DOUT[9:0] outputs. FLASH Output Flash output. Synchronization pulse for external light source. Can be left floating if not used. VPP Supply Power supply used to program one-time programmable (OTP) memory. VDD_TX Supply Digital PHY power supply. Digital power supply for the serial interface. VAA Supply Analog power supply. VAA_PIX Supply Analog power supply for the pixel array. AGND Supply Analog ground. VDD Supply Digital core power supply. VDD_IO Supply I/O power supply. DGND Supply Common ground for digital and I/O. VDD_PLL Supply PLL power supply. |
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