5

128Mb: x8DDR400 SDRAM

Micron Technology, Inc., reserves the right to change products or specifications without notice.

128Mbx8DDR400.p65 – Rev. A (1/30/02-B)

©2002, Micron Technology, Inc.

128Mb: x8

DDR400 SDRAM Addendum

PREVIEW

READ LATENCY

The READ latency is the delay, in clock cycles,

between the registration of a READ command and the

availability of the first bit of output data. The latency

should be set to 3 clocks, as shown in the CAS Latency

Diagram and Mode Register Definition Diagram.

If a READ command is registered at clock edge n,

and the latency is m clocks, the data will be available

nominally coincident with clock edge n + m.

Reserved states should not be used as unknown

operation or incompatibility with future versions may

result.

CK

CK#

COMMAND

DQ

DQS

CL = 3

READ

NOP

NOP

NOP

Burst Length = 4 in the cases shown

Shown with nominal tAC and nominal tDSDQ

T0

T1

T2

T2n

T3

T3n

DON’T CARE

TRANSITIONING DATA

CAS Latency

Diagram

Mode Register Definition

Diagram

M3 = 0

Reserved

2

4

8

Reserved

Reserved

Reserved

Reserved

M3 = 1

Reserved

2

4

8

Reserved

Reserved

Reserved

Reserved

Operating Mode

Normal Operation

Normal Operation/Reset DLL

All other states reserved

0

1

-

0

0

-

0

0

-

0

0

-

0

0

-

Valid

Valid

-

0

1

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Reserved

Reserved

3

Reserved

Reserved

Reserved

Reserved

Burst Length

M0

0

1

0

1

0

1

0

1

Burst Length

CAS Latency BT

0*

A9

A7 A6 A5 A4 A3

A8

A2 A1 A0

Mode Register (Mx)

Address Bus

97

6

5

4

3

82

1

0

M1

0

0

1

1

0

0

1

1

M2

0

0

0

0

1

1

1

1

M3

M4

0

1

0

1

0

1

0

1

M5

0

0

1

1

0

0

1

1

M6

0

0

0

0

1

1

1

1

M6-M0

M8 M7

Operating Mode

A10

BA0 A11

BA1

10

11

12

13

0*

* M13 and M12 (BA0 and BA1)

must be “0, 0” to select the

base mode register (vs. the

extended mode register).

M9

M10

M11