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MT28F800B3VG-9B Datasheet(PDF) 11 Page - Micron Technology

Part # MT28F800B3VG-9B
Description  FLASH MEMORY
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Manufacturer  MICRON [Micron Technology]
Direct Link  http://www.micron.com
Logo MICRON - Micron Technology

MT28F800B3VG-9B Datasheet(HTML) 11 Page - Micron Technology

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11
8Mb Smart 3 Boot Block Flash Memory
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Q10_3.p65 – Rev. 3, Pub. 10/01
©2001, Micron Technology, Inc.
8Mb
SMART 3 BOOT BLOCK FLASH MEMORY
ISM STATUS REGISTER
The 8-bit ISM status register (see Table 2) is polled
to check for WRITE or ERASE completion or any related
errors. During or following a WRITE, ERASE or ERASE
SUSPEND, a READ operation outputs the status register
contents on DQ0–DQ7 without prior command. While
the status register contents are read, the outputs are not
be updated if there is a change in the ISM status unless
OE# or CE# is toggled. If the device is not in the write,
erase, erase suspend or status register read mode, READ
STATUS REGISTER (70h) can be issued to view the status
register contents.
All of the defined bits are set by the ISM, but only
the ISM and erase suspend status bits are reset by the
ISM. The erase, write and VPP status bits must be cleared
using CLEAR STATUS REGISTER. If the VPP status bit
(SR3) is set, the CEL does not allow further WRITE or
ERASE operations until the status register is cleared.
This enables the user to choose when to poll and clear
the status register. For example, the host system may
perform multiple BYTE WRITE operations before check-
ing the status register instead of checking after each
individual WRITE. Asserting the RP# signal or power-
ing down the device also clears the status register.
STATUS
BIT #
STATUS REGISTER BIT
DESCRIPTION
SR7
ISM STATUS (ISMS)
The ISMS bit displays the active status of the state machine during
1 = Ready
WRITE or BLOCK ERASE operations. The controlling logic polls this
0 = Busy
bit to determine when the erase and write status bits are valid.
SR6
ERASE SUSPEND STATUS (ESS)
Issuing an ERASE SUSPEND places the ISM in the suspend mode
1 = ERASE suspended
and sets this and the ISMS bit to “1.” The ESS bit remains “1”
0 = ERASE in progress/completed
until an ERASE RESUME is issued.
SR5
ERASE STATUS (ES)
ES is set to “1” after the maximum number of ERASE cycles is
1 = BLOCK ERASE error
executed by the ISM without a successful verify. ES is only cleared
0 = Successful BLOCK ERASE
by a CLEAR STATUS REGISTER command or after a RESET.
SR4
WRITE STATUS (WS)
WS is set to “1” after the maximum number of WRITE cycles is
1 = WORD/BYTE WRITE error
executed by the ISM without a successful verify. WS is only cleared
0 = Successful WORD/BYTE WRITE
by a CLEAR STATUS REGISTER command or after a RESET.
SR3
VPP STATUS (VPPS)
VPPS detects the presence of a VPP voltage. It does not monitor VPP
1 = No VPP voltage detected
continuously, nor does it indicate a valid VPP voltage. The VPP pin
0 = VPP present
is sampled for 3.3V or 5V after WRITE or ERASE CONFIRM is given.
VPPS must be cleared by CLEAR STATUS REGISTER or by a RESET.
SR0-2
RESERVED
Reserved for future use.
Table 2
Status Register Bit Definitions
ISMS
ESS
ES
WS
VPPSR
765
43
2–0


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