11

2Mb Smart 3 Boot Block Flash Memory

Micron Technology, Inc., reserves the right to change products or specifications without notice.

F48.p65 – Rev. 1/00

©2000, Micron Technology, Inc.

2Mb

SMART 3 BOOT BLOCK FLASH MEMORY

COMMAND SET

To simplify writing of the memory blocks, the

MT28F002B3 and MT28F200B3 incorporate an ISM

that controls all internal algorithms for the WRITE and

ERASE cycles. An 8-bit command set is used to control

the device. Details on how to sequence commands are

provided in the Command Execution section. Table 1

lists the valid commands.

ISM STATUS REGISTER

The 8-bit ISM status register (see Table 2) is polled to

check for WRITE or ERASE completion or any related

errors. During or following a WRITE, ERASE or ERASE

SUSPEND, a READ operation will output the status

register contents on DQ0-DQ7 without prior com-

mand. While the status register contents are read, the

outputs will not be updated if there is a change in the

ISM status unless OE# or CE# is toggled. If the device is

not in the write, erase, erase suspend or status register

read mode, READ STATUS REGISTER (70H) can be

issued to view the status register contents.

All of the defined bits are set by the ISM, but only the

ISM and erase suspend status bits are reset by the ISM.

(SR3) is set, the CEL will not allow further WRITE or

ERASE operations until the status register is cleared.

This allows the user to choose when to poll and clear

the status register. For example, the host system may

perform multiple BYTE WRITE operations before check-

ing the status register instead of checking after each

individual WRITE. Asserting the RP# signal or powering

down the device will also clear the status register.

Table 2

Status Register

STATUS

BIT #

STATUS REGISTER BIT

DESCRIPTION

SR7

ISM STATUS

The ISMS bit displays the active status of the state machine during

1 = Ready

WRITE or BLOCK ERASE operations. The controlling logic polls this

0 = Busy

bit to determine when the erase and write status bits are valid.

SR6

ERASE SUSPEND STATUS

Issuing an ERASE SUSPEND places the ISM in the suspend mode

1 = ERASE suspended

and sets this and the ISMS bit to “1.” The ESS bit will remain “1” until

0 = ERASE in progress/completed

an ERASE RESUME is issued.

SR5

ERASE STATUS

ES is set to “1” after the maximum number of ERASE cycles is

1 = BLOCK ERASE error

executed by the ISM without a successful verify. ES is only cleared

0 = Successful BLOCK ERASE

by a CLEAR STATUS REGISTER command or after a RESET.

SR4

WRITE STATUS

WS is set to “1” after the maximum number of WRITE cycles is

1 = WORD/BYTE WRITE error

executed by the ISM without a successful verify. WS is only cleared

0 = Successful WORD/

by a CLEAR STATUS REGISTER command or after a RESET.

BYTE WRITE

SR3

must be cleared by CLEAR STATUS REGISTER or by a RESET.

SR0-2

RESERVED

Reserved for future use.