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MT28C3214P2NFL Datasheet(PDF) 5 Page - Micron Technology |
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MT28C3214P2NFL Datasheet(HTML) 5 Page - Micron Technology |
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5 / 42 page  5 2 Meg x 16 Page Flash 256K x 16 SRAM Combo Memory Micron Technology, Inc., reserves the right to change products or specifications without notice. MT28C3214P2FL_4.p65 – Rev. 4, Pub. 4/02 ©2002, Micron Technology, Inc. 2 MEG x 16 PAGE FLASH 256K x 16 SRAM COMBO MEMORY BALL DESCRIPTIONS 66-BALL FBGA NUMBERS SYMBOL TYPE DESCRIPTION A3, A4, A5, A6, A0–A20 Input Address Inputs: Inputs for the addresses during READ and WRITE A7, A8, B3, B4, operations. Addresses are internally latched during READ and WRITE B5, B6, E5, G3, cycles. Flash: A0–A20; SRAM: A0–A17. G4, G5, G6, G7, G8, G9, H4, H5, H6 H7 F_CE# Input Flash Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is disabled and goes into standby power mode. H9 F_OE# Input Flash Output Enable: Enables Flash output buffers when LOW. When F_OE# is HIGH, the output buffers are disabled. C3 F_WE# Input Flash Write Enable: Determines if a given cycle is a Flash WRITE cycle. F_WE# is active LOW. D4 F_RP# Input Reset. When F_RP# is a logic LOW, the device is in reset, which drives the outputs to High-Z and resets the WSM. When F_RP# is a logic HIGH, the device is in standard operation. When F_RP# transitions from logic LOW to logic HIGH, the device resets all blocks to locked and defaults to the read array mode. E3 F_WP# Input Flash Write Protect. Controls the lock down function of the flexible locking feature. G10 S_CE1# Input SRAM Chip Enable1: Activates the SRAM when it is LOW. HIGH level deselects the SRAM and reduces the power consumption to standby levels. D8 S_CE2 Input SRAM Chip Enable2: Activates the SRAM when it is HIGH. LOW level deselects the SRAM and reduces the power consumption to standby levels. F5 S_OE# Input SRAM Output Enable: Enables SRAM output buffers when LOW. When S_OE# is HIGH, the output buffers are disabled. B8 S_WE# Input SRAM Write Enable: Determines if a given cycle is an SRAM WRITE cycle. S_WE# is active LOW. F3 S_LB# Input SRAM Lower Byte: When LOW, it selects the SRAM address lower byte (DQ0–DQ7). F4 S_UB# Input SRAM Upper Byte: When LOW, it selects the SRAM address upper byte (DQ8–DQ15). B7, B9, B10, DQ0–DQ15 Input/ Data Inputs/Outputs: Input array data on the second CE# and WE# C7, C8, C9, Output cycle during PROGRAM command. Input commands to the command C10, D7, E6, user interface when CE# and WE# are active. Output data when CE# E8, E9, E10, and OE# are active. F7, F8, F9, F10 (continued on next page) |
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