BOTTOM VIEW

TOP VIEW

1

2

3

4

5

6

7

8

SIDE VIEW

EN

VCON

FB

SGND

5

6

7

8

1

2

3

4

VREF

VIN

PGND

VOUT

PAD

(SGND)

LMZ10500

www.ti.com

SNVS723F – OCTOBER 2011 – REVISED FEBRUARY 2015

5 Pin Configuration and Functions

8-Pin

SIL Package

Pin Functions

PIN

I/O

DESCRIPTION

NAME

NO.

EN

1

I

Enable Input. Set this digital input higher than 1.2 V for normal operation. For shutdown, set low.

Pin is internally pulled up to VIN and can be left floating for always-on operation.

VCON

2

I

Output voltage control pin. Connect to analog voltage from resisitve divider or DAC/controller to

SGND to provide noise filtering.

FB

3

I

SGND

4

I

Ground for analog and control circuitry. Connect to PGND at a single point.

VOUT

5

O

Output Voltage. Connected to one pin of the integrated inductor. Connect output filter capacitor

between VOUT and PGND.

PGND

6

I

Power ground for the power MOSFETs and gate-drive circuitry.

VIN

7

I

Voltage supply input. Connect ceramic capacitor between VIN and PGND as close as possible to

these two pins. Typical capacitor values are between 4.7 µF and 22 µF.

VREF

8

O

2.35 V voltage reference output. Typically connected to VCON pin through a resistive divider to set

the output voltage.

PAD

I

The center pad underneath the SIL0008A package is internally tied to SGND. This pad should be

connected to the ground plane for improved thermal performance.

Copyright © 2011–2015, Texas Instruments Incorporated

Submit Documentation Feedback

3

Product Folder Links: LMZ10500