7

ML6401

Note:

Circuit in dashed lines is an optional 1175 input

network which can be replaced with circuits in

Figure 1 or 2.

CLK

D7

D6

D5

D4

D3

D2

D1

D0

OE

VRTS

VRT

VIN+

VRBS

VRB

12

11

10

9

8

7

6

5

4

3

2

1

13

14

15

16

17

18

19

20

21

22

23

24

1175 PINOUT

+5V

HC04

CLOCK IN

CLK

C10

0.1

µF

C4

0.1

µF

C3

47

µF

C1

470

µF

C6

47

µF

C9

47

µF

+

+

+

+

R10

75

Ω

C11

0.1

µF

C12

0.1

µF

C7

47

µF

C2

10

µF

C13

10pF

C8

0.1

µF

+12V

R8

100

Ω

R9

5k

Ω

R4

1k

Ω

R1

120

Ω

R2

180

Ω

R7*

5k

Ω

POT

R5

2k

Ω

R3

500

Ω

C5

0.1

µF

Q3

Q2

Q1

–12V

*POT R7 WILL HAVE TO BE ADJUSTED

LSB

MSB

+

+

3. CXD1175 — Connect VRBS to VRB and leave VRTS

open while driving VRT with an external voltage. This

allows similar functionality to #2 preceding, but the

bias voltage (code 0) will move when the full scale

range is changed.

ML6401 — Open pin 16, drive pin 17 externally, and

connect pin 22 to pin 23. The full scale range will be

2

× pin 17 volts, and the bias (code 128) will occur at

1.5 volts (internally generated from bandgap). The full

scale range of the A/D must be kept below 4 volts, but

the part is only specified for full scale range of 2 volts.

Figure 3. Replacement for 1175.

4. CXD1175 — Connect VRTS to VRT and leave VRBS

open while driving VRB with an external voltage. This

allows similar functionality to #2 preceding, but the

bias voltage (code 0) will move when the full scale

range is changed.

ML6401 — Connect pin 16 to pin 17, open pin 22 and

drive pin 23 externally. The full scale range will be 2

volts (internally generated from bandgap), and the bias

(code 128) will occur at pin 23

±2% volts.