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ML4851 Datasheet(PDF) 8 Page - Micro Linear Corporation |
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ML4851 Datasheet(HTML) 8 Page - Micro Linear Corporation |
8 / 9 page 8 ML4851 July, 2000 DATASHEET TOPLAYER BOTTOMLAYER ML4851-3 ML4851-5 DESIGN CONSIDERATIONS (Continued) Figure 6. Sample PC Board Layout Table 1. Maximum Output Current and Efficiency vs. VIN VIN IOUT (mA) EFFICIENCY PERCENTAGE L = 10µH 1.0 24.2 78.3 1.5 68.0 79.9 2.0 123.1 80.3 L = 18µH 1.0 15.7 82.3 1.5 43.3 84.8 2.0 80.4 85.7 2.5 125.3 86.2 3.0 169.9 86.5 3.5 236.9 87.0 L = 33µH 1.0 9.1 83.5 1.5 24.8 87.0 2.0 47.4 88.6 2.5 74.5 89.5 3.0 106.9 90.3 3.5 147.5 90.8 4.0 190.0 91.4 4.5 227.8 92.1 L = 56µH 1.0 5.5 80.1 1.5 13.9 85.9 2.0 28.5 88.9 2.5 45.7 90.3 3.0 67.1 91.4 3.5 92.5 92.3 4.0 122.1 92.6 4.5 149.6 93.8 VIN IOUT (mA) EFFICIENCY PERCENTAGE L = 10µH 1.0 45.8 77.6 1.5 108.3 77.7 2.0 184.1 77.9 L = 18µH 1.0 30.1 82.5 1.5 70.9 83.5 2.0 125.5 83.9 2.5 185.7 84.5 3.0 243.4 85.4 L = 33µH 1.0 17.6 86.0 1.5 42.7 87.8 2.0 76.1 88.7 2.5 120.4 89.7 3.0 159.6 90.7 L = 56µH 1.0 10.6 85.2 1.5 25.9 89.1 2.0 47.6 90.8 2.5 75.8 92.0 3.0 108.0 93.1 RR V AB IN MIN =× − () . 02 1 (6) LAYOUT Good PC board layout practices will ensure the proper operation of the ML4851. Important layout considerations include: n Use adequate ground and power traces or planes n Keep components as close as possible to the ML4851 n Use short trace lengths from the inductor to the VL pin and from the output capacitor to the VOUT pin n Use a single point ground for the ML4851 PWR GND pin and the input and output capacitors, and connect GND to PWR GND with a separate trace A sample PC board layout is shown in Figure 6. |
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