9

ML4668

Since the amplifier has a differential input, two capacitors

of equal value are required. If the signal driving the input

is single ended, one of the coupling capacitors can be tied

The internal amplifier has a lowpass filter built-in to band

limit the input signal which in turn will improve the signal

to noise ratio.

Although the input is AC coupled, the offset voltage

within

the amplifier will be present at the amplifier’s output. This

error, a DC feedback loop is incorporated. This negative

pole it creates can effect the stability of the feedback loop.

To avoid stability problems, the value of this capacitor

should be at least 10 times larger than the input coupling

capacitors.

Figure 4.

The comparator is a high-speed, differential zero crossing

detector that slices and accurately digitizes the receive

signal. The output of the comparator is fed in parallel into

both the receive squelch circuit and the loopback MUX.

LINK DETECT CIRCUIT AND LOW LIGHT

The link detect circuit monitors the input signal and

determines when the input falls below a preset voltage

level. When the input falls below a preset voltage, the

ML4668 goes into the Low Light state. In the Low Light

state the transmitter is disabled, but continues sending the

1MHz idle signal, the loopback is disabled, the receiver is

disabled, and the

LMON LED pin goes to high shutting off

the

LMON LED. To return to the Link Pass state, the

optical receiver power must be 20% higher than the shut-

off state. This built-in hysteresis adds stability to the Link

Monitor circuit. Once the receiver power threshold is

exceeded, the ML4668 waits 250ms to 750ms, then

checks to see that Tx+. Tx– is idle and no data is being

received before re-enabling the transmitter, receiver,

loopback circuit, and lighting up the

LMON LED.

receiver. The ML4668 is capable of exceeding the

10BASE-FL specifications for sensitivity. The sensitivity is

dependent on the layout of the PC board. A good low

noise layout will exceed the 10BASE-FL specifications,

while a poor layout will fail to meet the sensitivity and

BER spec.

The threshold generator shifts the reference voltage at

coefficient matching that of the limiting amplifier. The

peak input threshold) is:

(2)

bit errors at a receive power level of –32.5dBm average.

One procedure to determine the sensitivity of a receiver is

to start at the lowest optical power level and gradually

increase the optical power until the BER is met. In this

case the Link Detect circuit must not disable the receiver

just above the power level that meets the BER

specification. This way the receiver will shut-off before the

BER is exceeded.

However if greater sensitivity is required the circuit in

with these two resistors available. This will allow potential

future adjustments without board revisions.

The response time of the Link Detect circuit is set by the

switched on if the input exceeds the set threshold for a

time given by:

T=

A

700

µ

(3)

To switch the link from on to off, the above time will be

doubled. A value of 0.05

µF will meet to 10BASE-FL

specifications.

REF

THRESH

GEN

VREF

VTHADJ

R1

R2

Figure 5.