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6ED003L02-F2 Datasheet(PDF) 4 Page - Infineon Technologies AG

Part # 6ED003L02-F2
Description  Signal interlocking of every phase to prevent cross-conduction
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Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

6ED003L02-F2 Datasheet(HTML) 4 Page - Infineon Technologies AG

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EiceDRIVER™
6ED003L06-F2, 6ED003L02-F2
datasheet
4
<Revision 2.7>, 15.04.2015
Table of Contents
1
Overview .............................................................................................................................................5
2
Blockdiagram......................................................................................................................................6
3
Pin configuration, description, and functionality ...........................................................................7
3.1
Low Side and High Side Control Pins (Pin 2, 3, 4, 5, 6, 7) ..................................................................7
3.2
EN (Gate Driver Enable, Pin 10) ..........................................................................................................8
3.3
/FAULT (Fault Feedback, Pin 8) ..........................................................................................................8
3.4
ITRIP and RCIN (Over-Current Detection Function, Pin 9, 11) ...........................................................9
3.5
VCC, VSS and COM (Low Side Supply, Pin 1, 12,13) ........................................................................9
3.6
VB1,2,3 and VS1,2,3 (High Side Supplies, Pin 18, 20, 22, 24, 26, 28) ...............................................9
3.7
LO1,2,3 and HO1,2,3 (Low and High Side Outputs, Pin 14, 15, 16, 19, 23, 27) .................................9
4
Electrical Parameters.......................................................................................................................10
4.1
Absolute Maximum Ratings ...............................................................................................................10
4.2
Required operation conditions ...........................................................................................................11
4.3
Operating Range ................................................................................................................................11
4.4
Static logic function table ...................................................................................................................12
4.5
Static parameters ...............................................................................................................................12
4.6
Dynamic parameters ..........................................................................................................................14
5
Timing diagrams...............................................................................................................................15
6
Package .............................................................................................................................................18
6.1
PG-DSO-28 ........................................................................................................................................18
6.2
PG-TSSOP-28....................................................................................................................................19
List of Figures
Figure 1
Typical Application ...............................................................................................................................6
Figure 2
Block diagram for 6ED003L06-F2 / 6ED003L02-F2 ............................................................................6
Figure 3
Pin Configuration of 6ED003L06-F2 and 6ED003L02-F2 ...................................................................7
Figure 4
Input pin structure.................................................................................................................................7
Figure 5
Input filter timing diagram .....................................................................................................................8
Figure 6
EN pin structures..................................................................................................................................8
Figure 7
/FAULT pin structures ..........................................................................................................................8
Figure 8
Timing of short pulse suppression .....................................................................................................15
Figure 9
Timing of internal deadtime ................................................................................................................15
Figure 10
Enable delay time definition ...............................................................................................................15
Figure 11
Input to output propagation delay times and switching times definition .............................................16
Figure 12
Operating areas..................................................................................................................................16
Figure 13
ITRIP-Timing ......................................................................................................................................16
Figure 14
ITRIP input filter time..........................................................................................................................17
Figure 15
Package drawing................................................................................................................................18
Figure 16
PCB reference layout .........................................................................................................................18
Figure 17
Package drawing................................................................................................................................19
Figure 18
PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint19
List of Tables
Table 1
Members of 6ED family
– 2
nd generation .............................................................................................5
Table 2
Pin Description .....................................................................................................................................7
Table 3
Abs. maximum ratings........................................................................................................................10
Table 4
Required Operation Conditions ..........................................................................................................11
Table 5
Operating range .................................................................................................................................11
Table 6
Static parameters ...............................................................................................................................12
Table 7
Dynamic parameters ..........................................................................................................................14
Table 8
Data of reference layout .....................................................................................................................19


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