SW

VBST

EN

VFB

GND

VO

7

5

1

VIN

VIN

VREG5

EN

Logic

SW

PGND

Protection

Logic

Ref

SS

UVLO

UVLO

Softstart

SS

REF

TSD

Ref

VREG5

4

SS

2

VIN

Ceramic

Capacitor

6

SGND

PGND

SW

PGND

ZC

8

3

OV

+25%

OV

SGND

PWM

Control Logic

1 Shot

VREG5

XCON

VREG5

OCP

TPS54339E

www.ti.com

SLVSBM0A – DECEMBER 2012 – REVISED DECEMBER 2012

PIN FUNCTIONS (continued)

PIN

DESCRIPTION

NAME

NO.

5.5 V power supply output. A capacitor (typical 0.47 µF) should be connected to GND. VREG5 is not active

VREG5

6

when EN is low.

EN

7

Enable input control. EN is active high and must be pulled up to enable the device.

SS

8

Soft-start control. An external capacitor should be connected to GND.

Exposed

Thermal pad of the package. Must be soldered to achieve appropriate dissipation. Must be connected to

Back side

Thermal Pad

GND.

FUNCTIONAL BLOCK DIAGRAM

Copyright © 2012, Texas Instruments Incorporated

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