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TPS54317 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS54317 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 21 page PIN1 0.1250 0.0120 24x 0.0320 24x 0.1182 0.0197 0.1620 0.0400 0.0400 6x0.013DIA EXPOSED POWERPAD AREA TPS54317 SLVS619B – NOVEMBER 2005 – REVISED SEPTEMBER 2009 ..................................................................................................................................... www.ti.com Figure 11. TPS54317 PCB Layout LAYOUT CONSIDERATIONS FOR THERMAL PERFORMANCE For operation at full rated load current, the analog ground plane must provide adequate heat dissipating area. A 3 inch by 3 inch plane of 1 ounce copper is recommended, though not mandatory, depending on ambient temperature and airflow. Most applications have larger areas of internal ground plane available, and the PowerPAD should be connected to the largest area available. Additional areas on the top or bottom layers also help dissipate heat, and any area available should be used when 3 A or greater operation is desired. Connection from the exposed area of the PowerPAD to the analog ground plane layer should be made using 0.013 inch diameter vias to avoid solder wicking through the vias. Six vias should be in the PowerPAD area additional vias located under the device package may be added to enhance thermal performance. The vias under the package, but not in the exposed thermal pad area, can be increased in size to 0.018. Figure 12. Recommended Land Pattern for 24-Pin QFN PowerPAD 10 Submit Documentation Feedback Copyright © 2005–2009, Texas Instruments Incorporated Product Folder Link(s): TPS54317 |
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