Control Logic

On/Off time

Minimun On/Off

OVP/UVP,

Discharge

Control

XCON

OCP

ERR

COMP

OV

UV

ENx

VOx

PGNDx

LLx

VOx

Fault

Sdn

V50K

VBSTx

DRVHx

SWx

VREG5

VREG5

DRVLx

PGNDx

V5FILT

GND

Ref

VFBx

TRIPx

–30%

+15%

SSx

GND

IصA

LL

PGNDx

1 Shot

TPS53125

www.ti.com

SLVS947C – OCTOBER 2009 – REVISED AUGUST 2014

Functional Block Diagrams (continued)

8.3 Feature Description

8.3.1 PWM Operation

The main control loop of the TPS53125 is an adaptive on-time pulse width modulation (PWM) controller using a

proprietary D-CAP2™ mode control. D-CAP2™ mode control combines constant on-time control with an internal

compensation circuit for pseudo-fixed frequency and low external component count configuration with both low

ESR and ceramic output capacitors. It is stable even with virtually no ripple at the output.

At the beginning of each cycle, the synchronous high-side MOSFET is turned on. After an internal one-shot timer

expires, this MOSFET is turned off. When the feedback voltage falls below the reference voltage, the one-shot

timer is reset and the high-side MOSFET is turned back on. The one shot is set by the converter input voltage

VIN, and the output voltage VO, to maintain a pseudo-fixed frequency over the input voltage range. An internal

ramp is added to the reference voltage to simulate output ripple, eliminating the need for ESR induced output

ripple from D-CAP mode control.

8.3.2 Drivers

Each channel of the TPS53125 contains two high-current resistive MOSFET gate drivers. The low-side driver is a

MOSFET whose source is connected to PGND. The high-side driver is a floating SWx referenced VBST powered

voltage during the high-side driver ON time, a capacitor is placed from SWx to VBSTx. Each driver draws

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