TPS53114

SLVS887C – APRIL 2009 – REVISED AUGUST 2014

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Feature Description (continued)

8.3.2 Drivers

The TPS53114 contains two high-current resistive MOSFET gate drivers. The low-side driver is a ground

whose source is connected to PGND. The high-side driver is a floating SW referenced VBST powered driver

during the high-side driver ON time, a capacitor is placed from SW to VBST. Each driver draws average current

To prevent cross-conduction, there is a narrow dead-time when both high-side and low-side drivers are OFF

between each driver transition. During this time the inductor current is carried by one of the MOSFET's body

diodes.

8.3.3 PWM Frequency and Adaptive On-time Control

TPS53114 employs adaptive on-time control scheme and does not have a dedicated on board oscillator.

TPS53114 runs with pseudo-constant frequency by using the input voltage and output voltage to set the on-time

one-shot timer. The on-time is inversely proportional to the input voltage and proportional to the output voltage.

Therefore, when the duty ratio is VOUT/VIN, the frequency is constant.

8.3.4 5-Volt Regulator

The TPS53114 has an internal 5-V low-dropout (LDO) Regulator to provide a regulated voltage for all both

drivers and the IC's internal logic. A high-quality 4.7-

μF or greater ceramic capacitor from VREG5 to GND is

required to stabilize the internal regular. An internal 10-

Ω resistor from VREG5 filters the regulator output to the

IC's analog and logic input voltage, V5FILT. An additional high-quality 1.0-

μF ceramic capacitor is required from

V5FILT to GND to filter switching noise from VREG5.

8.3.5 Soft Start

The TPS53114 has a programmable soft start . When the EN pin becomes high, 2.0-

μA current begins charging

the capacitor which is connected SS pin to GND. Smooth control of the output voltage is maintained during start

up.

8.3.6

Pre-bias Support

The TPS53114 supports pre-bias start-up without sinking current from the output capacitor. When enabled, the

low-side driver is held off until the soft start commands a voltage higher than the pre-bias level (internal soft start

becomes greater than feedback voltage (VFB)), then the TPS53114 slowly activates synchronous rectification by

limiting the first DRVL pulses with a narrow on-time. This limited on-time is then incremented on a cycle-by-cycle

basis until it coincides with the full 1-D off-time. This scheme prevents the initial sinking of current from the pre-

control loop is given time to transition from pre-biased start-up to normal mode operation.

8.3.7 Switching Frequency Selection

The TPS53114 allows the user to select from two different switching frequencies by connecting the FSEL pin to

V5FILT for a switching frequency of 700 KHz.

8.3.8 Output Discharge Control

The TPS53114 discharges the outputs when EN is low, or the controller is turned off by the protection functions

(OVP, UVP, UVLO, and thermal shutdown). The device discharges output using an internal 40-

Ω MOSFET which

is connected to VO and PGND. The external low-side MOSFET is not turned on during the output discharge

operation to avoid the possibility of causing negative voltage at the output. This discharge ensures that, on start,

the regulated voltage always initializes from 0 V.

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