3

Exposed

Thermal Pad

9

10

11

12

8

7

6

5

4

2

1

16

15

14

13

PVIN

PVIN

AVIN

SS/TR

SW

SW

SW

PG

TLV62150, TLV62150A

www.ti.com

SLVSB71D – FEBRUARY 2012 – REVISED AUGUST 2015

5 Device Comparison Table

PART NUMBER

OUTPUT VOLTAGE

POWER GOOD LOGIC LEVEL (EN=Low)

TLV62150

Adjustable

High Impedance

TLV62150A

Adjustable

Low

6 Pin Configuration and Functions

RGT Package

16-Pin VQFN

Top View

space

Pin Functions

I/O

DESCRIPTION

NAME

NO.

AGND

6

—

Analog Ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

AVIN

10

I

Supply voltage for control circuitry. Connect to same source as PVIN.

DEF

8

I

EN

13

I

FB

5

I

Voltage feedback. Connect resistive voltage divider to this pin.

FSW

7

I

Switching Frequency Select (Low

SW

1,2,3

O

Switch node, which is connected to the internal MOSFET switches. Connect inductor between SW and

output capacitor.

PG

4

O

Output power good (High = VOUT ready, Low = VOUT below nominal regulation) ; open drain (requires

pull-up resistor)

PGND

15,16

—

Power ground. Must be connected directly to the Exposed Thermal Pad and common ground plane.

PVIN

11,12

I

Supply voltage for power stage. Connect to same source as AVIN.

Soft-Start / Tracking Pin. An external capacitor connected to this pin sets the internal voltage reference rise

SS/TR

9

I

time. It can be used for tracking and sequencing.

VOS

14

I

Output voltage sense pin and connection for the control loop circuitry.

Exposed

Must be connected to AGND (pin 6), PGND (pin 15,16) and common ground plane. See the Layout

—

—

Thermal Pad

Example. Must be soldered to achieve appropriate power dissipation and mechanical reliability.

(1)

For more information about connecting pins, see Detailed Description and Application and Implementation sections.

(2)

An internal pull-down resistor keeps logic level low, if pin is floating.

(3)

Connect FSW to VOUT or PG in this case.

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