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TPS3700DSET Datasheet(PDF) 11 Page - Texas Instruments |
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TPS3700DSET Datasheet(HTML) 11 Page - Texas Instruments |
11 / 28 page Overvoltage Limit Undervoltage Limit V MON OUTB OUTA TPS3700 www.ti.com SBVS187D – FEBRUARY 2012 – REVISED JANUARY 2015 Feature Description (continued) Figure 15. Window Comparator Timing Diagram 8.3.4 Immunity to Input Terminal Voltage Transients The TPS3700 device is relatively immune to short voltage transient spikes on the input terminals. Sensitivity to transients depends on both transient duration and amplitude; see the Minimum Pulse Width vs Threshold Overdrive Voltage curve (Figure 7) in Typical Characteristics. 8.4 Device Functional Modes 8.4.1 Normal Operation (VDD > UVLO) When the voltage on VDD is greater than 1.8 V for at least 150 µs, the OUTA and OUTB signals correspond to the voltage on INA+ and INB– as listed in Table 1. 8.4.2 Undervoltage Lockout (V(POR) < VDD < UVLO) When the voltage on VDD is less than the device UVLO voltage, and greater than the power-on reset voltage, V(POR), the OUTA and OUTB signals are asserted and high impedance, respectively, regardless of the voltage on INA+ and INB–. 8.4.3 Power-On Reset (VDD < V(POR)) When the voltage on VDD is lower than the required voltage to internally pull the asserted output to GND (V(POR)), both outputs are in a high-impedance state. Copyright © 2012–2015, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Links: TPS3700 |
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