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FEDL9286-03 Datasheet(PDF) 6 Page - List of Unclassifed Manufacturers |
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FEDL9286-03 Datasheet(HTML) 6 Page - List of Unclassifed Manufacturers |
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6 / 37 page  FEDL9286-03 ML9286-xx 6/37 PIN DESCRIPTION PAD No Symbol Type Connects to Description 4～38 SEG1 to 35 O VFD tube anode electrode Fluorescent display tube anode electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH > –5.0 mA 39～58 COM1 to 20 O VFD tube grid electrode Fluorescent display tube grid electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH > –30.0 mA 2, 3 AD1, AD2 O VFD tube anode electrode Fluorescent display tube anode electrode drive output. Directly connected to fluorescent display tube and a pull-down resistor is not necessary. IOH > –10.0 mA 63,77 VDD — Power supply Power supply pin for internal logic. 1, 59, 60,80 VDISP — Power supply Power supply pin for driving fluorescent tubes. 61, 79 D-GND — Power supply D-GND pin for driver circuits of a VFD tube. Connect this pin to the external L-GND. 62, 78 L-GND — Power supply L-GND pin for logic circuits. Connect this pin to the external D-GND. 67 DA I Micro controller Serial data input. (Built-in Schmitt Circuit) Input from LSB. (positive logic) 68 CP I Micro controller Shift clock input. (Built-in Schmitt Circuit) Serial data is shifted on the rising edge of CP. 66 CS I Micro controller Chip select input. (Built-in Schmitt Circuit) Serial data transfer is disabled when CS pin is "H" level. 69 RESET I Micro controller Reset input. (Built-in Schmitt Circuit)"Low" initializes all the functions. For initial status see Reset Function. 75 OSC0 I 76 OSC1 O Crystal or ceramic resonator Pins for self-oscillation. Connect these pins to the crystal and capacitors or to the ceramic resonator and capacitors. The target oscillation frequency is 4.0 MHz. ( Note that the device includes the feed back resistor. See Application Circuit. ) 70 DO O — Serial data output pin for test mode. (positive logic) Do not use in normal operation. ( DO outputs “L” level in normal operation. ) 64 XOUT O Cascade connection Generate output 1/4 clock for OSC0. The main usage is to connect this pin to the OSC0 pin of the adjacent IC when the ML9286 is cascaded. 65 SYNCO O Cascade connection Frame sync signal output pin. A synchronous pulse is output from this pin immediately before the start of the frame. 74 SYNCI I Cascade connection Frame sync signal input pin. A synchronous pulse is input from this pin immediately before the start of the frame. 72 M/S — Cascade connection This pin is used for setting the master or salve. When M/S = Low, the ML9286 is master mode. When M/S = High, the ML9286 is slave mode. 73 DMY-GND O — The output pin to fix the adjacent input pin to the GND level. Use this pin only for this purpose. 71 DMY-VDD O — The output pin to fix the adjacent input pin to the VDD level. Use this pin only for this purpose. |
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