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TPS7A4101 Datasheet(PDF) 5 Page - Texas Instruments |
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TPS7A4101 Datasheet(HTML) 5 Page - Texas Instruments |
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5 / 23 page  TPS7A41 www.ti.com SBVS183A – DECEMBER 2011 – REVISED AUGUST 2015 6.5 Electrical Characteristics At TJ = –40°C to 125°C, VIN = VOUT(NOM) + 2 V or VIN = 7 V (whichever is greater), VEN = VIN, IOUT = 100 µA, CIN = 1 μF, COUT = 4.7 μF, and FB tied to OUT, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN Input voltage range 7 50 V VREF Internal reference TJ = 25°C, VFB = VREF, VIN = 9 V, IOUT = 25 mA 1.161 1.173 1.185 V Output voltage range(1) VIN ≥ VOUT(NOM) + 2 V VREF 48 V Nominal accuracy TJ = 25°C, VIN = 9 V, IOUT = 25 mA –1 1 %VOUT VOUT VOUT(NOM) + 2 V ≤ VIN ≤ 24 V (2) Overall accuracy –2.5 2.5 %VOUT 100 µA ≤ IOUT ≤ 50 mA ΔVO(ΔVI) Line regulation 7 V ≤ VIN ≤ 50 V 0.03 %VOUT ΔVO(ΔVL) Load regulation 100 µA ≤ IOUT ≤ 50 mA 0.31 %VOUT VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 20 mA 290 mV VDO Dropout voltage VIN = 17 V, VOUT(NOM) = 18 V, IOUT = 50 mA 0.78 1.3 V VOUT = 90% VOUT(NOM), VIN = 7 V, TJ ≤ 85°C 51 117 200 mA ILIM Current limit VOUT = 90% VOUT(NOM), VIN = 9 V 51 128 200 mA 7 V ≤ VIN ≤ 50 V, IOUT = 0 mA 25 65 μA IGND Ground current IOUT = 50 mA 25 μA ISHDN Shutdown supply current VEN = 0.4 V 4.1 20 μA I FB Feedback current(3) –0.1 0.01 0.1 µA IEN Enable current 7 V ≤ VIN ≤ 50 V, VIN = VEN 0.02 1 μA VEN_HI Enable high-level voltage 1.5 VIN V VEN_LO Enable low- level voltage 0 0.4 V VIN = 12 V, VOUT(NOM) = VREF, COUT = 10 μF, 58 μVRMS BW = 10 Hz to 100 kHz VNOISE Output noise voltage VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF, 73 μVRMS CBYP (4) = 10 nF, BW = 10 Hz to 100 kHz VIN = 12 V, VOUT(NOM) = 5 V, COUT = 10 μF, PSRR Power-supply rejection ratio 65 dB CBYP (4) = 10 nF, f = 100 Hz Shutdown, temperature increasing 170 °C TSD Thermal shutdown temperature Reset, temperature decreasing 150 °C Operating junction temperature TJ –40 125 °C range (1) To ensure stability at no-load conditions, a current from the feedback resistive network greater than or equal to 10 μA is required. (2) Maximum input voltage is limited to 24 V because of the package power dissipation limitations at full load (P ≈ (VIN – VOUT) × IOUT = (24 V – VREF) × 50 mA ≈ 1.14 W). The device is capable of sourcing a maximum current of 50 mA at higher input voltages as long as the power dissipated is within the thermal limits of the package plus any external heatsinking. (3) IFB > 0 flows out of the device. (4) CBYP refers to a bypass capacitor connected to the FB and OUT pins. 6.6 Dissipation Ratings DERATING FACTOR TA ≤ 25°C POWER TA = 70°C POWER TA = 85°C POWER BOARD PACKAGE RθJA RθJC ABOVE TA = 25°C RATING RATING RATING High-K(1) DGN 55.9°C/W 8.47°C/W 16.6 mW/°C 1.83 W 1.08 W 0.833 W (1) The JEDEC High-K (2s2p) board design used to derive this data was a 3-inch x 3-inch multilayer board with 2-ounce internal power and ground planes and 2-ounce copper traces on top and bottom of the board. Copyright © 2011–2015, Texas Instruments Incorporated Submit Documentation Feedback 5 |
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Similar Description - TPS7A4101_15 |
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