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TC820 Datasheet(PDF) 9 Page - Microchip Technology |
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TC820 Datasheet(HTML) 9 Page - Microchip Technology |
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9 / 28 page  © 2002 Microchip Technology Inc. DS21476B-page 9 TC820 In a simple dual slope converter, a complete conver- sion requires the integrator output to "ramp-up" from zero and "ramp-down" back to zero. A simple mathe- matical equation relates the input signal, reference volt- age, and integration time. EQUATION 3-1: For a constant VINT: EQUATION 3-2: FIGURE 3-1: BASIC DUAL SLOPE CONVERTER Accuracy in a dual slope converter is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inher- ent benefit of the dual slope technique is noise immu- nity. Noise spikes are integrated or averaged to zero during the integration periods, making integrating ADCs immune to the large conversion errors that plague successive approximation converters in high noise environments. Interfering signals, with frequency components at multiples of the averaging (integrating) period, will be attenuated (Figure 3-2). Integrating ADCs commonly operate with the signal integration period set to a multiple of the 50/60Hz power line period. FIGURE 3-2: NORMAL MODE REJECTION OF DUAL SLOPE CONVERTER 3.2 Analog Section In addition to the basic integrate and de-integrate dual slope phases discussed above, the TC820 design incorporates a "zero integrator output" phase and an "auto-zero" phase. These additional phases ensure that the integrator starts at 0V (even after a severe over range conversion), and that all offset voltage errors (buffer amplifier, integrator and comparator) are removed from the conversion. A true digital zero read- ing is assured without any external adjustments. A complete conversion consists of four distinct phases: 1. Zero Integrator Output 2. Auto-Zero 3. Signal Integrate 4. Reference De-integrate 3.2.1 ZERO INTEGRATOR OUTPUT PHASE This phase guarantees that the integrator output is at 0V before the system zero phase is entered, ensuring that the true system offset voltages will be compen- sated for even after an over range conversion. The duration of this phase is 500 counts plus the unused de-integrate counts. 3.2.2 AUTO-ZERO PHASE During the auto-zero phase, the differential input signal is disconnected from the measurement circuit by open- ing internal analog switches, and the internal nodes are shortedtoAnalogCommon(0VREF) toestablishazero input condition. Additional analog switches close a feedback loop around the integrator and comparator to permit comparator offset voltage error compensation. A voltage established on CAZ then compensates for inter- nal device offset voltages during the measurement cycle. The auto-zero phase residual is typically 10 µVto 15 µV. The auto-zero duration is 1500 counts. 1 RINTCINT tINT 0 VIN(t)dt = VREFtDEINT RINTCINT ∫ Where: VREF = Reference Voltage tINT = Integration Time tDEINT = De-integration Time VIN =VREF tDEINT tINT REF Voltage Analog Input Signal Display Switch Driver Control Logioc Clock Counter Polarity Control Phase Control VIN = VREF VIN = 1.2VREF Variable Reference Integrate Time Fixed Signal Integrate Time Integrator C Comparator R 30 20 10 0 0.1/T 1/T 10/T Input Frequency T = Measurement Period |
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