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PIC16LF628T Datasheet(PDF) 11 Page - Microchip Technology |
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PIC16LF628T Datasheet(HTML) 11 Page - Microchip Technology |
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11 / 160 page  © 1999 Microchip Technology Inc. Preliminary DS40300B-page 11 PIC16F62X TABLE 3-1: PIC16F62X PINOUT DESCRIPTION Name DIP/ SOIC Pin # SSOP Pin # I/O/P Type Buffer Type Description RA0/AN0 17 19 I/O ST Bi-directional I/O port/Analog comparator input RA1/AN1 18 20 I/O ST Bi-directional I/O port/Analog comparator input RA2/AN2/VREF 1 1 I/O ST Bi-directional I/O port/Analog comparator input/VREF out- put RA3/AN3/CMP1 2 2 I/O ST Bi-directional I/O port/Analog comparator input/compara- tor output RA4/T0CKI/CMP2 3 3 I/O ST Bi-directional I/O port/Can be configured as T0CKI/com- parator output RA5/MCLR/THV 4 4 I ST Input port/master clear (reset input/programming voltage input. When configured as MCLR, this pin is an active low reset to the device. Voltage on MCLR/THV must not exceed VDD during normal device operation. RA6/OSC2/CLKOUT 15 17 I/O ST Bi-directional I/O port/Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In ER mode, OSC2 pin outputs CLKOUT which has 1/4 the fre- quency of OSC1, and denotes the instruction cycle rate. RA7/OSC1/CLKIN 16 18 I/O ST Bi-directional I/O port/Oscillator crystal input/external clock source input. ER biasing pin. RB0/INT 6 7 I/O TTL/ST(1) Bi-directional I/O port/external interrupt. Can be software programmed for internal weak pull-up. RB1/RX/DT 7 8 I/O TTL/ST (3) Bi-directional I/O port/ USART receive pin/synchronous data I/O. Can be software programmed for internal weak pull-up. RB2/TX/CK 8 9 I/O TTL/ST (3) Bi-directional I/O port/ USART transmit pin/synchronous clock I/O. Can be software programmed for internal weak pull-up. RB3/CCP1 9 10 I/O TTL/ST (4) Bi-directional I/O port/Capture/Compare/PWM I/O. Can be software programmed for internal weak pull-up. RB4/PGM 10 11 I/O TTL/ST (5) Bi-directional I/O port/Low voltage programming input pin. Wake-up from SLEEP on pin change. Can be software programmed for internal weak pull-up. When low voltage programming is enabled, the interrupt on pin change and weak pull-up resistor are disabled. RB5 11 12 I/O TTL Bi-directional I/O port/Wake-up from SLEEP on pin change. Can be software programmed for internal weak pull-up. RB6/T1OSO/T1CKI 12 13 I/O TTL/ST (2) Bi-directional I/O port/Timer1 oscillator output/Timer1 clock input. Wake up from SLEEP on pin change. Can be software programmed for internal weak pull-up. RB7/T1OSI 13 14 I/O TTL/ST (2) Bi-directional I/O port/Timer1 oscillator input. Wake up from SLEEP on pin change. Can be software programmed for internal weak pull-up. VSS 55,6 P — Ground reference for logic and I/O pins. VDD 14 15,16 P — Positive supply for logic and I/O pins. Legend: O = output I/O = input/output P = power — = Not used I = Input ST = Schmitt Trigger input TTL = TTL input I/OD =input/open drain output Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. Note 2: This buffer is a Schmitt Trigger input when used in serial programming mode. Note 3: This buffer is a Schmitt Trigger I/O when used in USART/Synchronous mode. Note 4: This buffer is a Schmitt Trigger I/O when used in CCP mode. Note 5: This buffer is a Schmitt Trigger input when used in low voltage program mode. |
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