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X28HC256PIZ-90 Datasheet(PDF) 6 Page - Intersil Corporation |
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X28HC256PIZ-90 Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 19 page X28HC256 6 FN8108.5 August 27, 2015 Submit Document Feedback Read Cycle tCE tRC ADDRESS CE OE WE DATA VALID tOE tLZ tOLZ tOH tAA tHZ tOHZ DATA I/O VIH HIGH Z DATA VALID FIGURE 3. READ CYCLE Write Cycle Limits PARAMETER SYMBOL MIN TYP (Note 10)MAX UNIT Write Cycle Time tWC (Note 11)3 5 ms Address Setup Time tAS 0ns Address Hold Time tAH 50 ns Write Setup Time tCS 0ns Write Hold Time tCH 0ns CE Pulse Width tCW 50 ns OE HIGH Setup Time tOES 0ns OE HIGH Hold Time tOEH 0ns WE Pulse Width tWP 50 ns WE HIGH Recovery (page write only) tWPH (Note 12) 50 ns Data Valid tDV 1µs Data Setup tDS 50 ns Data Hold tDH 0ns Delay to Next Write After Polling is True tDW (Note 12)10 µs Byte Load Cycle tBLC 0.15 100 µs NOTES: 10. Typical values are for TA = +25°C and nominal supply voltage. 11. tWC is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum time the device requires to automatically complete the internal write operation. 12. tWPH and tDW are periodically sampled and not 100% tested. |
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