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HSP50110JI-52 Datasheet(PDF) 5 Page - Intersil Corporation |
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HSP50110JI-52 Datasheet(HTML) 5 Page - Intersil Corporation |
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5 / 25 page  5 processing pipeline latency, and the latency of the part’s serial interfaces while conserving power. Note: the effective input sample rate to the internal processing elements is equal to the frequency with which ENI is asserted “low”. In Interpolated Input Mode, the ENI input is used to insert zeroes between the input data samples. This process increases the input sample rate to the processing elements which improves the time resolution of the processing chain. When ENI is sampled “high” by CLK, a zero is input into the processing pipeline. When ENI is sampled “low” the input data is fed into the pipeline. Note: Due to the nature of the rate change operation, consideration must be given to the scaling and interpolation filtering required for a particular rate change factor. In either the Gated or Interpolated Input Mode, the Synthesizer NCO is gated by the ENI input. This only allows clocking of the NCO when external samples are input to the processing pipeline. As a result, the NCO frequency must be set relative to the input sample rate, not the CLK rate (see Synthesizer/Mixer Section). NOTE: Only fixed interpolation rates should be used when operating the part in Interpolated Mode at the Input Controller. Input Level Detector The Input Level Detector generates a one-bit error signal for an external IF AGC filter and amp. The error signal is generated by comparing the magnitude of the input samples to a user programmable threshold. The HI/LO pin is then driven “high” or “low” depending the relationship of its magnitude to the threshold. The sense of the HI/LO pin is programmable so that a magnitude exceeding the threshold can either be represented as a “high” or “low” logic state. The threshold and the sense of the HI/LO pin are configured by loading the appropriate control registers via the Microprocessor Interface (see Tables 7 and 11). The high/low outputs can be integrated by an external loop filter to close an AGC loop. Using this method the gain of the loop forces the median magnitude of the input samples to the threshold. When the magnitude of half the samples are above the threshold and half are below, the error signal is integrated to zero by the loop filter. The algorithm for determining the magnitude of the complex input is given by: Mag(I,Q) = |I| + .375 x |Q| if |I| > |Q| (EQ. 1) or: Mag(I,Q) = |Q| + .375 x |I| if |Q| > |I|, (EQ. 2) Using this algorithm, the magnitude of complex inputs can be estimated with an error of <0.55dB or approximately 6.5%. For real inputs, the magnitude detector reduces to a an absolute value detector with negligible error. Note: an external AGC loop using the Input Level Detector may go unstable for a real sine wave input whose frequency is exactly one quarter of the sample rate (FS/4). The Level Detector responds to such an input by producing a square wave output with a 50% duty cycle for a wide range of thresholds. This square wave integrates to zero, indicating no error for a range of input signal amplitudes. Synthesizer/Mixer The Synthesizer/Mixer spectrally shifts the input signal of interest to DC for subsequent baseband filtering. This function is performed by using a complex multiplier to multiply the input with the output of a quadrature numerically controlled oscillator (NCO). The multiplier operation is: IOUT = IIN x cos (ωc) - QIN x sin (ωc) (EQ. 3) QOUT = IIN x sin (ωc) + QIN x cos (ωc) (EQ. 4) The complex multiplier output is rounded to 12 bits. For real inputs this operation is similar to that performed by a quadrature downconverter. For complex inputs, the Synthesizer/Mixer functions as a single-sideband or image reject mixer which shifts the frequency of the complex samples without generating images. The quadrature outputs of the NCO are generated by driving a sine/cosine lookup table with the output of a phase accumulator as shown in Figure 2. Each time the phase accumulator is clocked, its sum is incremented by the sum of SHIFT REG SYNC REG SYNC CFLD COF COFSYNC SIN/COS ROM REG REG TO COMPLEX MULTIPLIER SIN COS PH0-1 LOTP CARRIER FREQUENCY † LOAD CARRIER FREQUENCY † PHASE OFFSET † 32 32 8 2 10 10 MUX 0 COF MUX 0 LOAD † PHASE ACCUMULATOR CF COF ENABLE † R E G REG + REG + REG R E G R E G Controlled via microprocessor interface. † FIGURE 2. SYNTHESIZER NCO 11 HSP50110 |
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