TLS805B1SJV

Pin Configuration

Data Sheet

5

Rev. 1.0, 2015-02-05

3

Pin Configuration

3.1

Pin Assignment in PG-DSO-8 Package

Figure 2

Pin Configuration TLS805B1 in PG-DSO-8 package

3.2

Pin Definitions and Functions in PG-DSO-8 Package

Pin

Symbol

Function

1I

Input

It is recommended to place a small ceramic capacitor (e.g. 100 nF) to GND, close

to the IC terminals, in order to compensate line influences.

2N.C.

Not connected

3EN

Enable

Integrated pull-down resistor.

Enable the IC with high level input signal.

Disable the IC with low level input signal.

4GND

Ground

5N.C.

Not connected

6N.C.

Not connected

7ADJ

Voltage Adjustment

Connect an external voltage divider to determine the output voltage.

8Q

Output

Connect an output capacitor

C

values specified for its capacitance and ESR in Table 2 “Functional Range” on

Page 7.

Q

ADJ

N.C.

I

N.C.

EN

GND

N.C.

1

3

2

8

7

6

45