25AA640/25LC640/25C640

© 1997 Microchip Technology Inc.

Preliminary

DS21223A-page 9

3.5

Read Status Register (RDSR)

The RDSR instruction provides access to the status

register. The status register may be read at any time,

even during a write cycle. The status register is format-

ted as follows:

The Write-In-Process (WIP) bit indicates whether the

25xx640 is busy with a write operation. When set to a

‘1’ a write is in progress, when set to a ‘0’ no write is in

progress. This bit is read only.

The Write Enable Latch (WEL) bit indicates the status

of the write enable latch. When set to a ‘1’ the latch

allows writes to the array and status register, when set

to a ‘0’ the latch prohibits writes to the array and status

register. The state of this bit can always be updated via

the WREN or WRDI commands regardless of the state

of write protection on the status register. This bit is

read only.

The Block Protection (BP0 and BP1) bits indicate

which blocks are currently write protected. These bits

are set by the user issuing the WRSR instruction.

These bits are non-volatile.

See Figure 3-6 for RDSR timing sequence

3.6

Write Status Register(WRSR)

The WRSR instruction allows the user to select one of

four levels of protection for the array by writing to the

appropriate bits in the status register. The array is

divided up into four segments. The user has the ability

to write protect none, one, two, or all four of the seg-

ments of the array. The partitioning is controlled as

illustrated in Table 3-2.

The Write Protect Enable (WPEN) bit is a non-volatile

bit that is available as an enable bit for the WP pin.

The Write Protect (WP) pin and the Write Protect

Enable (WPEN) bit in the status register control the

programmable hardware write protect feature. Hard-

ware write protection is enabled when WP pin is low

and the WPEN bit is high. Hardware write protection is

disabled when either the WP pin is high or the WPEN

bit is low. When the chip is hardware write protected,

only writes to non-volatile bits in the status register are

disabled. See Table 3-3 for a matrix of functionality on

the WPEN bit.

See Figure 3-7 for WRSR timing sequence

TABLE 3-2:

ARRAY PROTECTION

FIGURE 3-6:

READ STATUS REGISTER SEQUENCE

FIGURE 3-7:

WRITE STATUS REGISTER SEQUENCE

7

6

5

4

3

2

1

0

WPEN

X

X

X

BP1

BP0

WEL

WIP

BP1

BP0

Array Addresses

Write Protected

0

0

none

0

1

upper 1/4

(1800h - 1FFFh)

1

0

upper 1/2

(1000h - 1FFFh)

1

1

all

(0000h - 1FFFh)

SO

SI

CS

9

10 11

12 13 14 15

1

1

0

0

0

0

0

0

7

6

5

4

2

1

0

instruction

data from status register

high impedance

SCK

0

2

3

4

5

6

7

1

8

3

SO

SI

CS

9

10 11

12 13 14 15

0

1

0

0

0

0

0

0

7

6

5

4

2

1

0

instruction

data to status register

high impedance

SCK

0

2

3

4

5

6

7

1

8

3