© 1996 Microchip Technology Inc.

DS21109E-page 5

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FIGURE 11-2: READ CHARACTERISTICS AT END OF ARRAY TIMING

TABLE 11-2:

READ CHARACTERISTICS AT END OF ARRAY

AC Test Load: 50 pF

Symbol

Parameter

Limits 3.0V

≤ Vcc ≤

6.0V

Limits 4.5V

≤ Vcc ≤

6.0V

Units

Conditions

Min.

Max.

Min.

Max.

CLK to Data Float Delay

—

50

—

50

ns

Notes 1, 2

CLK to CEO Delay

—

65

—

40

ns

CE to CEO Delay

—

45

—

40

ns

RESET/OE to CEO Delay

—

45

—

40

ns

Note 1: This parameter is periodically sampled and not 100% tested.

2: Float delays are measured with output pulled through 1k

RESET/OE

FIRST BIT

LAST BIT

CE

CLK

DATA

CEO