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ZL9101MIRZ Datasheet(PDF) 11 Page - Intersil Corporation |
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ZL9101MIRZ Datasheet(HTML) 11 Page - Intersil Corporation |
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11 / 67 page  ZL9101M 11 FN7669.5 February 12, 2015 Submit Document Feedback Functional Description I2C/SMBus Communications The ZL9101M provides an I2C/SMBus digital interface that enables the user to configure all aspects of the module operation as well as monitor the input and output parameters. The ZL9101M can be used with any I2C host device. In addition, the module is compatible with SMBus version 2.0. Pull-up resistors are required on the I2C/SMBus as specified in the SMBus 2.0 specification. The ZL9101M accepts most standard PMBus commands. When controlling the device with PMBus commands, it is recommended that the enable pin is tied to SGND. The SMBus device address and VOUT_MAX are the only parameters that must be set by external pins. All other device parameters can be set via the I2C/SMBus. The device address is set using the SA pin. VOUT_MAX is determined as 10% greater than the voltage set by the VSET pin. Standard 1% resistor values are used between the respective pin and SGND. Output Voltage Selection The output voltage may be set to a voltage between 0.6V and 3.6V provided that the input voltage is higher than the desired output voltage by an amount sufficient to prevent the device from exceeding its maximum duty cycle specification. The VSET pin is used to set the output voltage to levels as shown in Table 1. The RSET resistor is placed between the VSET pin and SGND. The output voltage may also be set to any value between 0.6V and 3.6V using a PMBus command over the I2C/SMBus interface. The RSET resistor program places an upper limit in output voltage setting through PMBUS programming to 10% above the value set by the resistor. Soft-start Delay and Ramp Times It may be necessary to set a delay from when an enable signal is received until the output voltage starts to ramp to its target value. In addition, the designer may wish to precisely set the time required for VOUT to ramp to its target value after the delay period has expired. These features may be used as part of an overall in-rush current management strategy or to precisely control how fast a load IC is turned on. The ZL9101M gives the system designer several options for precisely and independently controlling both the delay and ramp time periods. The soft-start delay period begins when the EN pin is asserted and ends when the delay time expires. The soft-start delay and ramp times are set to a custom values via the I2C/SMBus interface. When the delay time is set to 0ms, the device begins its ramp-up after the internal circuitry has initialized (approximately 2ms). When the soft-start ramp period is set to 0ms, the output ramps up as quickly as the output load capacitance and loop settings allow. It is generally recommended to set the soft-start ramp to a value greater than 500µs to prevent inadvertent fault conditions due to excessive in-rush current. Power-Good The ZL9101M provides a Power-Good (PG) signal that indicates the output voltage is within a specified tolerance of its target level and no fault condition exists. By default, the PG pin asserts if the output is within 10% of the target voltage. These limits and the polarity of the pin may be changed via the I2C/SMBus interface. A PG delay period is defined as the time from when all conditions within the ZL9101M for asserting PG are met to when the PG pin is actually asserted. This feature is commonly used instead of using an external reset controller to control external digital logic. By default, the ZL9101M PG delay is set equal to the soft-start ramp time setting. Therefore, if the soft-start ramp time is set to 10ms, the PG delay is set to 10ms. The PG delay may be set independently of the soft-start ramp using the I2C/SMBus. TABLE 1. OUTPUT VOLTAGE RESISTOR SETTINGS VOUT (V) RSET (kΩ) 0.60 10 0.65 11 0.70 12.1 0.75 13.3 0.80 14.7 0.85 16.2 0.90 17.8 0.95 19.6 1.00 21.5 1.05 23.7 1.10 26.1 1.15 28.7 1.20 31.6 1.25 34.8 1.30 38.3 1.40 42.2 1.50 46.4 1.60 51.1 1.70 56.2 1.80 61.9 1.90 68.1 2.00 75 2.10 82.5 2.20 90.9 2.30 100 2.50 110 2.80 121 3.00 133 3.30 147 TABLE 1. OUTPUT VOLTAGE RESISTOR SETTINGS (Continued) VOUT (V) RSET (kΩ) |
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