2

Ordering Information

PART NUMBER

TEMP.

PACKAGE

PKG.

DWG. #

HI1-5042-2

-55 to 125

16 Ld CERDIP

F16.3

HI1-5043-2

-55 to 125

16 Ld CERDIP

F16.3

HI1-5043-5

0 to 75

16 Ld CERDIP

F16.3

HI3-5043-5

0 to 75

16 Ld PDIP

E16.3

HI3-5043-5Z

(See Note)

0 to 75

16 Ld PDIP*

(Pb-free)

F16.3

HI9P5043-5

0 to 75

16 Ld SOIC

M16.15

HI9P5043-5Z

(See Note)

0 to 75

16 Ld SOIC

(Pb-free)

M16.15

HI1-5047-5

0 to 75

16 Ld CERDIP

F16.3

HI1-5049-5

0 to 75

16 Ld CERDIP

F16.3

HI1-5051-2

-55 to 125

16 Ld CERDIP

F16.3

HI1-5051-5

0 to 75

16 Ld CERDIP

F16.3

HI3-5051-5

0 to 75

16 Ld PDIP

E16.3

HI3-5051-5Z

(See Note)

0 to 75

16 Ld PDIP *

(Pb-free)

E16.3

HI9P5051-9

-40 to 85

16 Ld SOIC

M16.15

HI9P5051-9Z

(See Note)

-40 to 85

16 Ld SOIC

(Pb-free)

M16.15

*

Pb-free PDIPs can be used for through hole wave solder

processing only. They are not intended for use in Reflow solder

processing applications.

NOTE: Intersil Pb-free products employ special Pb-free material

sets; molding compounds/die attach materials and 100% matte tin

plate termination finish, which are RoHS compliant and compatible

with both SnPb and Pb-free soldering operations. Intersil Pb-free

products are MSL classified at Pb-free peak reflow temperatures that

meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Single Control

SPDT

HI-5042 (50

Ω)

4PST

HI-5047 (50

Ω)

NOTE:

Unused pins may be internally connected. Ground all

unused pins.

Dual Control

DUAL SPDT

HI-5043 (50

Ω), HI-5051 (25Ω)

DUAL DPST

HI-5049 (25

Ω)

NOTE:

Unused pins may be internally connected. Ground all

unused pins.

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

V-

V+

A

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

V-

V+

A

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

V-

V+

14

15

16

9

13

12

11

10

1

2

3

4

5

7

6

8

V-

V+

HI-5042 thru HI-5051