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24LCS52 Datasheet(PDF) 4 Page - Microchip Technology

Part No. 24LCS52
Description  2K 2.5V I 2 C Serial EEPROM with Software Write Protect
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Maker  MICROCHIP [Microchip Technology]
Homepage  http://www.microchip.com
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24LCS52
DS21166B-page 4
Preliminary
© 1996 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24LCS52 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as transmitter, and a device
receiving data as receiver. The bus has to be controlled
by a master device which generates the serial clock
(SCL), controls the bus access, and generates the
START and STOP conditions, while the 24LCS52
works as slave. Both master and slave can operate as
transmitter or receiver but the master device deter-
mines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is
not busy.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last six-
teen will be stored when doing a write operation. When
an overwrite does occur it will replace data in a first in
first out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this case,
the slave must leave the data line HIGH to enable the
master to generate the STOP condition.
3.6
Device Addressing
A control byte is the first byte received following the
START condition from the master device. The first part
of the control byte consists of a 4-bit control code which
is set to 1010 for normal read and write operations and
0110 for writing to the write protect register. The control
byte is followed by three chip select bits (A2, A1, A0).
The chip select bits allow the use of up to eight
24LCS52 devices on the same bus and are used to
determine which device is accessed. The chip select
bits in the control byte must correspond to the logic lev-
els on the corresponding A2, A1 and A0 pins for the
device to respond. The device will not acknowledge if
you attempt a read command with the control code set
to 0110.
Note:
The 24LCS52 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
(A)
(B)
(C)
(D)
(A)
(C)
SCL
SDA
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION




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