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24AA00-ESN Datasheet(PDF) 4 Page - Microchip Technology |
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24AA00-ESN Datasheet(HTML) 4 Page - Microchip Technology |
4 / 18 page 24AA00/24LC00/24C00 DS21178D-page 4 2003 Microchip Technology Inc. 2.0 PIN DESCRIPTIONS 2.1 SDA Serial Data This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pull-up resistor to VCC (typical 10 k Ω for 100 kHz, 2 kΩ for 400 kHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.2 SCL Serial Clock This input is used to synchronize the data transfer from and to the device. 2.3 Noise Protection The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. 3.0 FUNCTIONAL DESCRIPTION The 24XX00 supports a bidirectional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, and a device receiving data as a receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access, and generates the Start and Stop conditions, while the 24XX00 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. 4.4 Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is theoretically unlimited. |
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