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24LC21-P Datasheet(PDF) 7 Page - Microchip Technology |
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24LC21-P Datasheet(HTML) 7 Page - Microchip Technology |
7 / 12 page © 1996 Microchip Technology Inc. DS21095F-page 7 24LC21 3.1.6 SLAVE ADDRESS After generating a START condition, the bus master transmits the slave address consisting of a 7-bit device code (1010) for the 24LC21, followed by three don’t care bits. The eighth bit of slave address determines if the master device wants to read or write to the 24LC21 (see Figure 3-5). The 24LC21 monitors the bus for its corresponding slave address all the time. It generates an acknowledge bit if the slave address was true and it is not in a pro- gramming mode. FIGURE 3-5: CONTROL BYTE ALLOCATION Operation Control Code Chip Select R/W Read 1010 XXX 1 Write 1010 XXX 0 SLAVE ADDRESS 101 0X X X R/W A START READ/WRITE 4.0 WRITE OPERATION 4.1 Byte Write Following the start signal from the master, the slave address (4 bits), the don’t care bits (3 bits) and the R/W bit which is a logic low is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the address pointer of the 24LC21. After receiving another acknowledge signal from the 24LC21 the mas- ter device will transmit the data word to be written into the addressed memory location. The 24LC21 acknowl- edges again and the master generates a stop condi- tion. This initiates the internal write cycle, and during this time the 24LC21 will not generate acknowledge signals (see Figure 4-1). It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. 4.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24LC21 in the same way as in a byte write. But instead of generating a stop condi- tion the master transmits up to eight data bytes to the 24LC21 which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmitted a stop condition. After the receipt of each word, the three lower order address pointer bits are internally incremented by one. The higher order five bits of the word address remains con- stant. If the master should transmit more than eight words prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received an inter- nal write cycle will begin (see Figure 4-2). It is required that VCLK be held at a logic high level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. FIGURE 4-1: BYTE WRITE S P BUS ACTIVITY MASTER SDA LINE BUS ACTIVITY S T A R T S T O P CONTROL BYTE WORD ADDRESS DATA A C K A C K A C K VCLK |
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