24LC08B/16B MODULES

DS21224A-page 6

© 1997 Microchip Technology Inc.

6.0

WRITE OPERATIONS

6.1

Byte Write

Following the start condition from the master, the

device code (4 bits), the block address (3 bits), and the

R/W bit which is a logic low is placed onto the bus by

the master transmitter. This indicates to the addressed

slave receiver that a byte with a word address will follow

after it has generated an acknowledge bit during the

ninth clock cycle. Therefore the next byte transmitted by

the master is the word address and will be written into

the address pointer of the 24LC08B/16B. After receiv-

ing another acknowledge signal from the 24LC08B/16B

the master device will transmit the data word to be writ-

ten into the addressed memory location. The 24LC08B/

16B acknowledges again and the master generates a

stop condition. This initiates the internal write cycle,

and during this time the 24LC08B/16B will not generate

acknowledge signals (Figure 6-1).

6.2

Page Write

The write control byte, word address and the first data

byte are transmitted to the 24LC08B/16B in the same

way as in a byte write. But instead of generating a stop

condition the master transmits up to 16 data bytes to

the 24LC08B/16B which are temporarily stored in the

on-chip page buffer and will be written into the memory

after the master has transmitted a stop condition. After

the receipt of each word, the four lower order address

pointer bits are internally incremented by one. The

higher order seven bits of the word address remains

constant. If the master should transmit more than 16

words prior to generating the stop condition, the

address counter will roll over and the previously

received data will be overwritten. As with the byte write

operation, once the stop condition is received an inter-

nal write cycle will begin (Figure 6-2).

FIGURE 6-1:

BYTE WRITE

FIGURE 6-2:

PAGE WRITE

S

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

S

T

O

P

CONTROL

BYTE

WORD

ADDRESS

DATA

A

C

K

A

C

K

A

C

K

S

P

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

S

T

A

R

T

CONTROL

BYTE

WORD

ADDRESS (n)

DATA n

DATA n + 15

S

T

O

P

A

C

K

A

C

K

A

C

K

A

C

K

A

C

K

DATA n + 1