24AA65/24LC65/24C65

DS21073K-page 4

© 2008 Microchip Technology Inc.

TABLE 1-2:

AC CHARACTERISTICS

FIGURE 1-2:

BUS TIMING DATA

Parameter

Symbol

STD. Mode

FAST Mode

Units

Remarks

Min

Max

Min

Max

Clock frequency

—100

—

400

kHz

Clock high time

4000

—

600

—

ns

Clock low time

4700

—

1300

—

ns

SDA and SCL rise time

—

1000

—

300

ns

(Note 1)

SDA and SCL fall time

—

300

—

300

ns

(Note 1)

Start condition setup time

4000

—

600

—

ns

After this period the first

clock pulse is generated

Start condition setup time

4700

—

600

—

ns

Only relevant for

repeated Start condition

Data input hold time

0—

0

—

ns

Data input setup time

250

—

100

—

ns

Stop condition setup time

4000

—

600

—

ns

Output valid from clock

—

3500

—

900

ns

(Note 2)

Bus free time

4700

—

1300

—

ns

Time the bus must be

free before a new

transmission can start

—

250

20 + 0.1

250

ns

≤ 100 pF

Input filter spike suppression

(SDA and SCL pins)

50

—

50

—

ns

(Note 3)

Write cycle time

—

5

—

5

ms/page (Note 4)

Endurance

High Endurance Block

Rest of Array

10M

1M

—

—

10M

1M

—

—

cycles

25°C, (Note 5)

Note 1:

2:

As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

3:

noise and spike suppression. This eliminates the need for a Ti specification for standard operation.

4:

The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write

cache for total time.

5:

This parameter is not tested but ensured by characterization. For endurance estimates in a specific

application, please consult the Total Endurance™ Model which can be downloaded at www.microchip.com.

SCL

SDA

IN

SDA

OUT