ISL78235

3

FN8713.2

July 1, 2015

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Pin Configuration

ISL78235

(16 LD TQFN)

TOP VIEW

1

3

4

VIN

VDD

SYNC

2

7

5

6

FB

PGND

PG

8

11

9

10

16

13

15

14

12

SGND

PGND

EPAD

Pin Descriptions

PIN NUMBER

PIN NAME

DESCRIPTION

1, 16

VIN

Input supply voltage. Place a minimum of two 22µF low ESR ceramic capacitors from VIN to PGND as close

as possible to the IC for decoupling.

2

VDD

Input supply voltage for the logic circuitry. A 0.1µF high frequency decoupling ceramic capacitor should also

be placed close to the VDD and SGND pin. Connect to VIN pin.

3

PG

PG is an open-drain output for power-good indication. Use a 10kΩ to 100kΩ pull-up resistor connected from

PG to VIN. At power-up or EN high, PG rising edge is delayed by 1ms upon output voltage within regulation.

4

SYNC

Mode selection pin. Connect to logic high or input voltage VIN for forced PWM mode. Connect to logic low or

ground for PFM mode. Connect to an external function generator for synchronization with a positive edge

trigger. In external synchronization the ISL78235 operates in forced PWM mode. The transition to and from

internal oscillator to external synchronization is seamless and does not require disabling of the ISL78235.

There is an internal 1MΩ pull-down resistor to SGND to prevent an undefined logic state if SYNC pin is

floating.

5

EN

Regulator enable pin. Regulator is enabled when driven logic high. Regulator is shutdown and PHASE pin

discharge output capacitor when enable pin driven low.

6

FS

frequency of operation may be programmed between 500kHz to 4MHz. The switching frequency is 2MHz if

FS is connected to VIN.

7

SS

SS is used to adjust the soft-start time. Connect SS pin to SGND for internal 1ms soft-start time. Connect a

capacitor from SS to SGND to adjust the soft-start time. Do not use more than 33nF on the SS pin.

8

COMP

COMP is the output of the error amplifier if COMP is not connected to VDD. An external compensation

network must be used if COMP is not tied to VDD. If COMP is tied to VDD, the error amplifier output is

internally compensated. External compensation network across COMP and SGND may be required to

improve the loop compensation of the amplifier.

9

FB

The feedback network of the regulator, FB, is the negative input to the transconductance error amplifier. The

output voltage is set by an external resistor divider connected to FB. With a properly selected divider, the

output voltage can be set to any voltage between the power rail (reduced by converter losses) and the 0.6V

reference. In addition, the regulator power-good and undervoltage protection circuitry use FB to monitor the

regulator output voltage.

10

SGND

Signal ground, Connect to PGND.

11, 12

PGND

Power ground

13, 14, 15

PHASE

Switching node connections. Connect to one terminal of the inductor. This pin is discharged by a 100Ω

resistor when the device is disabled. See “Functional Block Diagram” on page 2 for more detail.

Exposed Pad

EPAD

The exposed pad must be connected to the SGND pin for proper electrical performance. Place as many vias

as possible under the pad connecting to SGND plane for optimal thermal performance.