SY87701V

3

Micrel

FUNCTIONAL DESCRIPTION

Clock Recovery

Clock Recovery, as shown in the block diagram generates

a clock that is at the same frequency as the incoming data

bit rate at the Serial Data input. The clock is phase aligned

by a PLL so that it samples the data in the center of the

data eye pattern.

The phase relationship between the edge transitions of

the data and those of the generated clock are compared by

a phase/frequency detector. Output pulses from the detector

indicate the required direction of phase correction. These

pulses are smoothed by an integral loop filter. The output of

the loop filter controls the frequency of the Voltage Controlled

Oscillator (VCO), which generates the recovered clock.

Frequency stability without incoming data is guaranteed

by an alternate reference input (REFCLK) that the PLL locks

onto when data is lost. If the Frequency of the incoming

signal varies by greater than approximately 1000ppm with

respect to the synthesizer frequency, the PLL will be declared

out of lock, and the PLL will lock to the reference clock.

The loop filter transfer function is optimized to enable the

PLL to track the jitter, yet tolerate the minimum transition

density expected in a received SONET data signal. This

transfer function yields a 30

µs data stream of continuous

1's or 0's for random incoming NRZ data.

The total loop dynamics of the clock recovery PLL

provides jitter tolerance which is better than the specified

tolerance in GR-253-CORE.

Lock Detect

The SY87701V contains a link fault indication circuit which

monitors the integrity of the serial data inputs. If the received

serial data fails the frequency test, the PLL will be forced to

lock to the local reference clock. This will maintain the correct

frequency of the recovered clock output under loss of signal

or loss of lock conditions. If the recovered clock frequency

deviates from the local reference clock frequency by more

than approximately 1000ppm, the PLL will be declared out

of lock. The lock detect circuit will pull the input data stream

in an attempt to reacquire lock to data. If the recovered

clock frequency is determined to be within approximately

1000ppm, the PLL will be declared in lock and the lock

detect output will go active.

RDOUTP, RDOUTN [Receive Data Output] Differential

PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent the recovered data from the input data stream

(RDIN). This recovered data is sampled on the rising edge

of RCLK.

RCLKP, RCLKN [Clock Output] Differential PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent the recovered clock used to sample the recovered

data (RDOUT).

TCLKP, TCLKN [Clock Output] Differential PECL.

These ECL 100K outputs (+3.3V or +5V referenced)

represent either the recovered clock (CLKSEL = HIGH) used

to sample the recovered data (RDOUT) or the transmit clock

of the frequency synthesizer (CLKSEL = LOW).

PLLSP, PLLSN [Clock Synthesis PLL Loop Filter]

External loop filter pins for the clock synthesis PLL.

PLLRP, PLLRN [Clock Recovery PLL Loop Filter]

External loop filter pins for the receiver PLL.

POWER & GROUND

GND

Ground

N/C

No Connect

NOTE: