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SY87701LHI Datasheet(PDF) 2 Page - Micrel Semiconductor |
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SY87701LHI Datasheet(HTML) 2 Page - Micrel Semiconductor |
2 / 12 page SY87701L 2 Micrel PIN DESCRIPTIONS INPUTS RDINP, RDINN [Serial Data Input] Differential PECL. These built-in line receiver inputs are connected to the differential receive serial data stream. An internal receive PLL recovers the embedded clock (RCLK) and data (RDOUT) information. The incoming data rate can be within one of eight frequency ranges depending on the state of the FREQSEL pins. See “Frequency Selection” Table. REFCLK [Reference Clock] TTL input. This input is used as the reference for the internal frequency synthesizer and the “training” frequency for the receiver PLL to keep it centered in the absence of data coming in on the RDIN inputs. CD [Carrier Detect] PECL Input. This input controls the recovery function of the Receive PLL and can be driven by the carrier detect output of optical modules or from external transition detection circuitry. When this input is HIGH the input data stream (RDIN) is recovered normally by the Receive PLL. When this input is LOW the data on the inputs RDIN will be internally forced to a constant LOW, the data outputs RDOUT will remain LOW, the Link Fault Indicator output LFIN forced LOW and the clock recovery PLL forced to lock onto the clock frequency generated from REFCLK. PLLSP TCLKN 18 11 PLLSN CLKSEL 17 12 GND PLLRP 16 13 GND PLLRN 15 14 1 VCCA LFIN DIVSEL1 RDINP RDINN FREQSEL1 REFCLK FREQSEL2 FREQSEL3 N/C 28 VCC CD DIVSEL2 RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP 27 26 25 24 23 22 21 20 19 2 3 4 5 6 7 8 9 10 Top View SOIC Z28-1 PIN CONFIGURATION 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 NC RDINP RDINN FREQSEL1 REFCLK FREQSEL2 FREQSEL3 NC RDOUTP RDOUTN VCCO RCLKP RCLKN VCCO TCLKP TCLKN 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 Top View EP-TQFP H32-1 FREQSEL1, ..., FREQSEL3 [Frequency Select] TTL Inputs. These inputs select the output clock frequency range as shown in the “Frequency Selection” Table. DIVSEL1, DIVSEL2 [Divider Select] TTL Inputs. These inputs select the ratio between the output clock frequency (RCLK/TCLK) and the REFCLK input frequency as shown in the “Reference Frequency Selection” Table. CLKSEL [Clock Select] TTL Input. This input is used to select either the recovered clock of the receiver PLL (CLKSEL = HIGH) or the clock of the frequency synthesizer (CLKSEL = LOW) to the TCLK outputs. OUTPUTS LFIN [Link Fault Indicator] TTL Output. This output indicates the status of the input data stream RDIN. Active HIGH signal is indicating when the internal clock recovery PLL has locked onto the incoming data stream. LFIN will go HIGH if CD is HIGH and RDIN is within the frequency range of the Receive PLL (1000ppm). LFIN is an asynchronous output. |
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