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TLV320DAC32 Datasheet(PDF) 9 Page - Texas Instruments |
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TLV320DAC32 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 70 page  th(WS) ts(WS) ts(DI) th(DI) WCLK BCLK SDIN tH(BCLK) tL(BCLK) tP(BCLK) ts(WS) th(WS) TIMING CHARACTERISTICS (1) TLV320DAC32 www.ti.com........................................................................................................................................ SLAS506B – NOVEMBER 2006 – REVISED DECEMBER 2008 TIMING CHARACTERISTICS (continued) All specifications typical at 25C, DVDD = 1.8 V IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX tH (BCLK) BCLK high period 70 35 ns tL (BCLK) BCLK low period 70 35 ns ts(WS) WCLK setup time 10 6 ns th(WS) WCLK hold time 10 6 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns Figure 4. DSP Timing in Slave Mode All specifications typical at 25C, DVDD = 1.8 V IOVDD = 1.1 V IOVDD = 3.3 V PARAMETER UNIT MIN MAX MIN MAX tH (BCLK) BCLK high period 70 35 ns tL (BCLK) BCLK low period 70 35 ns ts(WS) WCLK setup time 10 8 ns th(WS) WCLK hold time 10 8 ns ts(DI) DIN setup time 10 6 ns th(DI) DIN hold time 10 6 ns tr Rise time 8 4 ns tf Fall time 8 4 ns (1) All timing specifications are measured at characterization but not tested at final test. Copyright © 2006–2008, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Link(s): TLV320DAC32 |
Similar Part No. - TLV320DAC32_15 |
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Similar Description - TLV320DAC32_15 |
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