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TLV320AIC3254 Datasheet(PDF) 7 Page - Texas Instruments |
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TLV320AIC3254 Datasheet(HTML) 7 Page - Texas Instruments |
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7 / 53 page  TLV320AIC3254 www.ti.com SLAS549D – SEPTEMBER 2008 – REVISED NOVEMBER 2014 8 Specifications 8.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT AVDD to AVSS –0.3 2.2 V DVDD to DVSS –0.3 2.2 V Input voltage IOVDD to IOVSS –0.3 3.9 V LDOIN to AVSS –0.3 3.9 V Digital Input voltage to ground –0.3 IOVDD + 0.3 V Analog input voltage to ground –0.3 AVDD + 0.3 V Operating temperature range –40 85 °C Junction temperature (TJ Max) 105 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 8.2 Handling Ratings MIN MAX UNIT Tstg Storage temperature range –55 125 °C Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) –2 2 kV Electrostatic V(ESD) Charged device model (CDM), per JEDEC specification JESD22-C101, all discharge –750 750 V pins(2) (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 8.3 Recommended Operating Conditions MIN NOM MAX UNIT LDOIN 1.9 3.6 Referenced to AVSS (1) AVDD 1.5 1.8 1.95 Power Supply Voltage Range V IOVDD Referenced to IOVSS (1) 1.1 3.6 DVDD (2) Referenced to DVSS (1) 1.26 1.8 1.95 Clock divider uses fractional divide 10 20 MHz (D > 0), P = 1, DVDD ≥ 1.65V (Refer to the table in SLAA408, Maximum TLV320AIC3254 Clock Frequencies) PLL Input Frequency Clock divider uses integer divide 0.512 20 MHz (D = 0), P = 1, DVDD ≥ 1.65V (Refer to the table in SLAA408, Maximum TLV320AIC3254 Clock Frequencies) MCLK; Master Clock Frequency; DVDD ≥ 1.65V 50 MCLK Master Clock Frequency MHz MCLK; Master Clock Frequency; DVDD ≥ 1.26V 25 SCL SCL Clock Frequency 400 kHz 0.75 or CM = 0.75 V 0 0.530 Vpeak Audio input max ac signal swing AVDD-0.75(3) (IN1_L, IN1_R, IN2_L, IN2_R, IN3_L, 0.9 or IN3_R) CM = 0.9 V 0 0.707 Vpeak AVDD-0.9(3) LOL, LOR Stereo line output load resistance 0.6 10 k Ω Stereo headphone output load resistance Single-ended configuration 14.4 16 Ω HPL, HPR Headphone output load resistance Differential configuration 24.4 32 Ω CLout Digital output load capacitance 10 pF TOPR Operating Temperature Range –40 85 °C (1) All grounds on board are tied together to prevent voltage differences of more than 0.2V maximum for any combination of ground signals. (2) At DVDD values lower than 1.65V, the PLL does not function. Refer to the Maximum TLV320AIC3254 Clock Frequencies table in the TLV320AIC3254 Application Reference Guide (SLAA408) for details on maximum clock frequencies. (3) Whichever is smaller. Copyright © 2008–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: TLV320AIC3254 |
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