DESCRIPTION

FEATURES

JK FLIP-FLOP

PIN CONFIGURATION/BLOCK DIAGRAM

J

K

R

CLK

Qn+1

LL

L

Z

Qn

LH

L

Z

L

HL

L

Z

H

HH

L

Z

Qn

XX

H

X

L

NOTE:

1. Z = LOW-to-HIGH transition.

SOIC

TOP VIEW

1

2

3

45

6

7

8

J

Q

K

R

Q

R

CLK

J

K

Rev.: E

Amendment: /0

Issue Date:

August, 1998

SY10EL35

SY100EL35

s 525ps propagation delay

s 2.2GHz toggle frequency

s High bandwidth output transistions

s Internal 75K

s Available in 8-pin SOIC package

The SY10/100EL35 are high-speed JK Flip-Flops. The

J/K data enters the master portion of the flip-flop when

the clock is LOW and is transferred to the slave and,

thus, the outputs, upon a positive transition of the clock.

The reset pin is asynchronous and is activated with a

logic HIGH.

1