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X9251US24Z-2.7 Datasheet(PDF) 3 Page - Intersil Corporation |
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X9251US24Z-2.7 Datasheet(HTML) 3 Page - Intersil Corporation |
3 / 21 page X9251 3 FN8166.6 December 3, 2014 Submit Document Feedback Pin Configuration X9251 (24 LD SOIC/TSSOP) TOP VIEW Ordering Information PART NUMBER (Notes 2, 3) PART MARKING VCC LIMITS (V) POTENTIOMETER ORGANIZATION (kΩ) TEMP RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # X9251US24Z (Note 1) X9251US Z 5 ±10% 50 0 to +70 24 Ld SOIC (300 mil) M24.3 X9251US24IZ (Note 1) X9251US ZI -40 to +85 24 Ld SOIC (300 mil) M24.3 X9251UV24Z X9251UV Z 0 to +70 24 Ld TSSOP (4.4mm) M24.173 X9251UV24IZ X9251UV ZI -40 to +85 24 Ld TSSOP (4.4mm) M24.173 X9251US24IZ-2.7 (Note 1) X9251US ZG 2.7 to 5.5 -40 to +85 24 Ld SOIC (300 mil) M24.3 X9251US24Z-2.7 (Note 1) X9251US ZG 0 to +70 24 Ld SOIC (300 mil) M24.3 X9251UV24Z-2.7 X9251UV ZF 0 to +70 24 Ld TSSOP (4.4mm) M24.173 X9251UV24IZ-2.7 (Note 1) X9251UV ZG -40 to +85 24 Ld TSSOP (4.4mm) M24.173 NOTES: 1. Add "T1" suffix for tape and reel. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for X9251. For more information on MSL, please see tech brief TB363 SO A0 RW3 NC VCC RL0 1 2 3 4 5 6 7 8 9 10 24 23 22 21 20 19 18 17 16 15 HOLD SCK RL2 RH2 RW2 NC VSS RW1 RH1 RL1 X9251 RH3 14 13 11 12 RL3 RH0 RW0 CS A1 SI WP Pin Descriptions PIN (SOIC) SYMBOL FUNCTION 1 SO Serial Data Output for SPI bus 2 A0 Device Address for SPI bus (see Note 4) 3RW3 Wiper Terminal of DCP3 4RH3 High Terminal of DCP3 5RL3 Low Terminal of DCP3 7VCC System Supply Voltage 8RL0 Low Terminal of DCP0 9RH0 High Terminal of DCP0 10 RW0 Wiper Terminal of DCP0 11 CS SPI bus. Chip Select active low input 12 WP Hardware Write Protect - active low 13 SI Serial Data Input for SPI bus 14 A1 Device Address for SPI bus (see Note 4) 15 RL1 Low Terminal of DCP1 16 RH1 High Terminal of DCP1 17 RW1 Wiper Terminal of DCP1 18 VSS System Ground 20 RW2 Wiper Terminal of DCP2 21 RH2 High Terminal of DCP2 22 RL2 Low Terminal of DCP2 23 SCK Serial Clock for SPI bus 24 HOLD Device select. Pauses the SPI serial bus. 6, 19 NC No Connect NOTE: 4. A0 and A1 device address pins must be tied to a logic level. |
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