DESCRIPTION

FEATURES

Rev.: D

Amendment: /0

Rev. Date:

October, 1998

ClockWorks™

SY10E111AE/LE

SY100E111AE/LE

5V/3.3V 1:9 DIFFERENTIAL

CLOCK DRIVER (w/ENABLE)

s 5V and 3.3V power supply options

s 200ps part-to-part skew

s 50ps output-to-output skew

s Differential design

s Enable Input

s Voltage and temperature compensated outputs

s 75K

s Fully compatible with Motorola MC10/100E111

s Available in 28-pin PLCC package

The SY10/100E111AE/LE are low skew 1-to-9 differential

drivers designed for clock distribution in mind. The SY10/

100E111AE/LE's function and performance are similar to

the popular SY10/100E111, with the improvement of lower

jitter and the added feature of low voltage operation. It

accepts one signal input, which can be either differential or

out to 9 identical differential outputs. An enable input is

also provided such that a logic HIGH disables the device by

forcing all Q outputs LOW and all Q outputs HIGH.

The E111AE/LE is specifically designed, modeled and

produced with low skew as the key goal. Optimal design

and layout serve to minimize gate to gate skew within a

device, and empirical modeling is used to determine process

lot to lot. The net result is a dependable, guaranteed low

skew device.

To ensure that the tight skew specification is met it is

necessary that both sides of the differential output are

terminated into 50

Ω, even if only one side is being used. In

most applications, all nine differential pairs will be used

and therefore terminated. In the case where fewer that

nine pairs are used, it is necessary to terminate at least the

output pairs on the same package side as the pair(s) being

used on that side, in order to maintain minimum skew.

Failure to do this will result in small degradations of

propagation delay (on the order of 10-20ps) of the output(s)

being used which, while not being catastrophic to most

designs, will mean a loss of skew margin.

The E111AE/LE, as with most other ECL devices, can

This allows the E111AE/LE to be used for high performance

clock distribution in +5V/+3.3V systems. Designers can

take advantage of the E111AE/LE's performance to

distribute low skew clocks across the backplane or the

board. In a PECL environment, series or Thevenin line

terminations are typically used as they require no additional

power supplies. For systems incorporating GTL, parallel

termination offers the lowest power by taking advantage of

the 1.2V supply as terminating voltage.

BLOCK DIAGRAM

IN

IN

EN

1