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SY100S324FC Datasheet(PDF) 1 Page - Micrel Semiconductor |
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SY100S324FC Datasheet(HTML) 1 Page - Micrel Semiconductor |
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1 / 5 page  DESCRIPTION FEATURES s Max. propagation delay of 1.4ns s IEE min. of –70mA s Industry standard 100K ECL levels s Extended supply voltage option: VEE = –4.2V to –5.5V s Differential outputs s Voltage and temperature compensation for improved noise immunity s Internal 75K Ω input pull-down resistors s Twice as fast as Fairchild’s 324 s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S324 is a hex translator designed to convert TTL logic levels to 100K ECL levels. The inputs are TTL compatible with differential outputs that can either be used as an inverting/non-inverting translator or as differential line drivers. A common Enable (E), when LOW, holds all inverting outputs HIGH and holds all non- inverting outputs LOW. When used in the differential mode, due to its high common mode rejection, it overcomes voltage gradients between the TTL and ECL ground systems. The VEE and VTTL power may be applied in either order. LOW POWER HEX TTL-to-ECL TRANSLATOR PIN CONFIGURATIONS SY100S324 Rev.: F Amendment: /0 Issue Date: July, 1999 Pin Function D0–D5 Data Inputs E Enable Inputs Q0–Q5 Data Outputs Q0–Q5 Complementary Data Outputs VEES VEE Substrate VTTL TTL VCC Power Supply VCCA VCCO for ECL Outputs PIN NAMES 18 17 16 15 14 13 12 5 6 78 9 10 11 2 3 4 1 Top View Flatpack F24-1 24 23 22 21 20 19 D2 Q0 Q1 D1 Q0 Q1 D5 Q5 Q4 Q5 Q4 Q3 18 17 16 15 14 13 12 D0 VTTL E VEES VEE D3 D4 56789 10 11 26 27 28 1 2 3 4 Top View PLCC J28-1 25 24 23 22 21 20 19 Q2 VCC VCC VCCA VCCA Q3 Q2 BLOCK DIAGRAM D0 Q0 Q0 E D1 Q1 Q1 D2 Q2 Q2 D3 Q3 Q3 D4 Q4 Q4 D5 Q5 Q5 1 |
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