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KAD5514P-25Q48 Datasheet(PDF) 8 Page - Intersil Corporation |
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KAD5514P-25Q48 Datasheet(HTML) 8 Page - Intersil Corporation |
8 / 34 page 8 FN6804.2 September 10, 2009 Switching Specifications PARAMETER CONDITION SYMBOL MIN TYP MAX UNITS ADC OUTPUT Aperture Delay tA 375 ps RMS Aperture Jitter jA 60 fs Output Clock to Data Propagation Delay, LVDS Mode (Note 9) DDR, Rising Edge tDC -260 -50 120 ps DDR, Falling Edge tDC -160 10 230 ps SDR, Falling Edge tDC -260 -40 230 ps Output Clock to Data Propagation Delay, CMOS Mode (Note 9) DDR, Rising Edge tDC -220 -10 200 ps DDR, Falling Edge tDC -310 -90 110 ps SDR, Falling Edge tDC -310 -50 200 ps Latency (Pipeline Delay) L 8.5 cycles Overvoltage Recovery tOVR 1cycles SPI INTERFACE (Notes 10, 11) SCLK Period Write Operation tCLK 16 cycles (Note 10) Read Operation tCLK 66 cycles SCLK Duty Cycle (tHI/tCLK or tLO/tCLK) Read or Write 25 50 75 % CSB ↓ to SCLK↑ Setup Time Read or Write tS 1cycles CSB ↑ after SCLK↑ Hold Time Read or Write tH 3cycles Data Valid to SCLK ↑ Setup Time Write tDSW 1cycles Data Valid after SCLK ↑ Hold Time Write tDHW 3cycles Data Valid after SCLK ↓ Time Read tDVR 16.5 cycles Data Invalid after SCLK ↑ Time Read tDHR 3cycles Sleep Mode CSB ↓ to SCLK↑ Setup Time (Note 12) Read or Write in Sleep Mode tS 150 µs NOTES: 8. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD depending on desired function. 9. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most applications. Contact factory for more info if needed. 10. SPI Interface timing is directly proportional to the ADC sample period (4ns at 250Msps). 11. The SPI may operate asynchronously with respect to the ADC sample clock. 12. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup time (4ns min). KAD5514P |
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