8

FN6810.2

September 10, 2009

Pinout/Package Information

Sleep Mode CSB

↓ to SCLK↑ Setup Time

(Note 11)

Read or Write in Sleep Mode

150

µs

NOTES:

7. The Tri-Level Inputs internal switching thresholds are approximately .43V and 1.34V. It is advised to float the inputs, tie to ground or AVDD

depending on desired function.

8. The input clock to output clock delay is a function of sample rate, using the output clock to latch the data simplifies data capture for most

applications. Contact factory for more info if needed.

10. The SPI may operate asynchronously with respect to the ADC sample clock.

11. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal mode CSB setup

time (4ns min).

PARAMETER

CONDITION

SYMBOL

MIN

TYP

MAX

UNITS

Pin Descriptions

PIN #

LVDS [LVCMOS] NAME

LVDS [LVCMOS] FUNCTION

1, 6, 19, 24, 71

AVDD

1.8V Analog Supply

2-5, 17, 18, 28-35

DNC

Do Not Connect

7, 10-12, 72

AVSS

Analog Ground

8, 9

BINP, BINN

B-Channel Analog Input Positive, Negative

13, 14

AINN, AINP

A-Channel Analog Input Negative, Positive

15

VCM

Common Mode Output

16

CLKDIV

Clock Divider Control

20, 21

CLKP, CLKN

Clock Input True, Complement

22

OUTMODE

Output Mode (LVDS, LVCMOS)

23

NAPSLP

Power Control (Nap, Sleep modes)

25

RESETN

Power On Reset (Active Low, See “User-Initiated Reset” on page 15)

26, 45, 55, 65

OVSS

Output Ground

27, 36, 56

OVDD

1.8V Output Supply

37

D0N

[NC]

LVDS Bit 0 (LSB) Output Complement

[NC in LVCMOS]

38

D0P

[D0]

LVDS Bit 0 (LSB) Output True

[LVCMOS Bit 0]

39

D1N

[NC]

LVDS Bit 1 Output Complement

[NC in LVCMOS]

40

D1P

[D1]

LVDS Bit 1 Output True

[LVCMOS Bit 1]

41

D2N

[NC]

LVDS Bit 2 Output Complement

[NC in LVCMOS]

42

D2P

[D2]

LVDS Bit 2 Output True

[LVCMOS Bit 2]

43

D3N

[NC]

LVDS Bit 3 Output Complement

[NC in LVCMOS]

44

D3P

[D3]

LVDS Bit 3 Output True

[LVCMOS Bit 3]

KAD5610P