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KAD5510P-12Q48 Datasheet(PDF) 10 Page - Intersil Corporation |
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KAD5510P-12Q48 Datasheet(HTML) 10 Page - Intersil Corporation |
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10 / 31 page  KAD5510P 10 FN7693.2 May 2, 2011 Timing Diagrams FIGURE 2. DDR LVDS TIMING DIAGRAM (See “Digital Outputs” on page 18) FIGURE 3. DDR CMOS TIMING DIAGRAM (See “Digital Outputs” on page 18) LATENCY = L CYCLES tDC tPD tA SAMPLE N tCPD INP INN CLKN CLKP CLKOUTN CLKOUTP ODD BITS N-L N-L ODD BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 EVEN BITS EVEN BITS EVEN BITS D[8/6/4/2/0]P D[8/6/4/2/0]N N SAMPLE N tDC tPD tA INP INN CLKN CLKOUT CLKP D[8/6/4/2/0] LATENCY = L CYCLES ODD BITS N-L N-L ODD BITS ODD BITS EVEN BITS N-L + 1 N-L + 1 N-L + 2 N-L + 2 EVEN BITS EVEN BITS EVEN BITS N tCPD |
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