DESCRIPTION

The SY100EL92 is a triple LVPECL-to-PECL or PECL-

to-LVPECL translator. The device receives standard PECL

signals and translates them to differential LVPECL output

signals (or vice versa). SY100EL92 can also be used as a

differential line receiver for PECL-to-PECL or LVPECL-to-

LVPECL signals. However, please note that for the latter

we will need two different power supplies. Please refer to

Function Table for more details.

output should be connected to the D input and the active

designed to act as a switching reference for the SY100EL92

under single ended input conditions. As a result, the pin

can only source/sink 0.5mA of current.

To accomplish the PECL-to-LVPECL level translation,

supply, and GND is connected to the system ground plane.

a 0.01

µF capacitor.

To accomplish the LVPECL-to-PECL level translation,

the SY100EL92 requires three power rails as well. The 5.0V

5V.

Under open input conditions, the D input will be biased

GND. This condition will force the "Q" output low, ensuring

stability.

FEATURES

TRIPLE LVPECL-TO-PECL

OR PECL-TO-LVPECL

TRANSLATOR

SY100EL92

Rev.: D

Amendment: /0

Issue Date: January, 1999

Function

Vcc

Vcco

PECL-to-LVPECL

5.0V

3.3V

5.0V

LVPECL-to-PECL

5.0V

5.0V

3.3V

PECL-to-PECL

5.0V

5.0V

5.0V

LVPECL-to-LVPECL

5.0V

3.3V

3.3V

FUNCTION TABLE

Pin

Function

Dn

PECL / LVPECL Inputs

PECL / LVPECL Outputs

PECL / LVPECL Reference Voltage Output

GND

Common Ground Rail

PIN NAMES

PIN CONFIGURATION/BLOCK DIAGRAM

SOIC

TOP VIEW

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

GND

1